Source Files Page (Simulation Export Properties Dialog Box)

Use this page of the Simulation Export Properties dialog box to specify the top-level FPGA VI and the signals to export to the waveform viewer.

This page includes the following components:

Option Description
Project Files Displays a list of items under the current target in the Project Explorer window.
Top-Level VI Specifies which VI is the top-level VI. Select a VI from the Project Files list and click the Add Item button to add the VI as the top-level VI.
Signals to Populate in Waveform Specifies the types of signals you want to export for easier reference in the waveform viewer.
  • clip—Specifies to export CLIP signals.You must set the simulation behavior of CLIP before you can simulate CLIP signals.
  • nipi—Specifies to export signals from IP Integration Nodes.You must set the simulation behavior of the node before you can simulate the signals.
  • eio—Specifies to export signals from FPGA I/O Nodes.
  • topLvlCtrlsInds—Specifies to export signals from the controls and indicators in the top-level VI.