Additional Clock Status Signal Settings Page (Configure Component-Level IP Wizard)

Use this page of the Configure Component-Level IP wizard to view and change information about clock status signals in the IP.

Click the Create file or the Modify File button in the Component-Level IP page of the FPGA Target Properties dialog box to display the Configure Component-Level IP wizard.

This page includes the following components:

Option Description
HDL Name Displays the name of the clock status signal in the VHDL file.
Clock Status Type Indicates the type of clock status signal. LabVIEW determines the type based on the direction of the signal. Available status types are Derived Clocks Valid and Source Clock Ready.
Associated Clock Displays the LabVIEW name of the clock associated with the clock status signal.
Available Clock Displays a list of available clocks. Use this list to specify the clock associated with the clock status signal.