When you create a simulation export, you can specify the types of signals you are investigating so that they show up in the waveform viewer in LabVIEW-specific groupings. These groupings help you determine which signal corresponds to a component on the LabVIEW block diagram.

The main groups of signals to appear in the waveform viewer are the following:

• Top-level controls and indicators
• I/O
• CLIP top-level port signals
• IP Integration Node top-level port signals

Within the main groups, the waveform viewer also shows implicit signals, such as clocks, the enable chain, register update logic, registers, and block diagram wires. The enable chain enforces the LabVIEW dataflow paradigm, so it is useful as a starting point for determining how a signal fits into the overall execution order of the FPGA VI. You can see only resources that are related directly to block diagram signals.

Tip Use the VHDL names for block diagram objects to correspond these objects with signals in the waveform viewer. VHDL names appear at the bottom of the Context Help window.