Reset Signals and Behavior Page (Xilinx IP Node Properties Dialog Box)

Use this page to specify the ports in sequential IP that behave as asynchronous or synchronous reset signals.

Access this page by double-clicking a Xilinx IP node. If the node is on a supported target and is configured already, you can right-click the node and select Configure»Reset Signals and Behavior from the shortcut menu.

This page includes the following components:

Option Description
Reset Signals Contains options that relate to reset signals.
  • Synchronous reset signal(s)—Specifies the port(s) in the IP that behave as synchronous reset signals.
  • Asynchronous reset signal—Specifies the port in the IP that behaves as an asynchronous reset signal. If the IP does not contain this port, select No Asynchronous Reset from this pull-down list.
  • Active logic level—Specifies the active logic level of the asynchronous reset signal. This option is available only when you specify an asynchronous reset signal for the IP.
  • High—Specifies that the active logic level is high.
  • Low—Specifies that the active logic level is low.
  • sclr cycles—Specifies the number of clock cycles for which LabVIEW asserts the Synchronous reset signal(s) during a reset. If the IP has multiple synchronous reset signals that need different durations, enter the longest duration here.
  • sclr cycles—Specifies the number of clock cycles for which LabVIEW asserts the Asynchronous reset signal during a reset. The clock is running within the reset duration.

    The value must be 0 for this IP to be used when the build specification is configured to allow the removal of implicit enable signals because the Asynchronous reset signal will assert and deassert before the clock starts running. The value must also be 0 if this clock is used with external clocks that might stop during reset. If an IP requires a running clock during asynchronous reset, such as for IP that use built-in FIFOs, and the design requires the removal of implicit enable signals, consider creating a local asynchronous reset, and prevent diagram access to or from the IP while this local reset is asserted.
Reset IP Specifies the situation(s) in which LabVIEW resets the IP Integration Node.
  • Before first call—Specifies that LabVIEW resets the IP Integration Node before the first call to the FPGA VI.
  • Compile or load—

    Specifies that LabVIEW resets the IP only when the FPGA VI compiles or downloads to the FPGA.

    If you choose this option and the IP does not support asynchronous resets, the IP does not reset even if you invoke the Reset method. When the IP does reset, it might operate on garbage data, including metastable values. To mitigate these issues, ensure that your application does not depend on the values this IP returns immediately after resetting.
Feedback Displays warnings, errors, and configuration information.