Basic Signal Settings Page (Configure Component-Level IP Wizard)

Use this page of the Configure Component-Level IP wizard to specify the names and data types of block diagram terminals that correspond to VHDL ports in the component-level IP (CLIP).

Click the Create File or Modify File button in the Component-Level IP page of the FPGA Target Properties dialog box to display the Configure Component-Level IP wizard.

This page includes the following components:

Option Description
HDL Name Displays the name of the signal in the VHDL file.
LabVIEW Name Displays the name that LabVIEW uses to identify the signal. By default, the LabVIEW name matches the HDL name. You can enter a new name in the LabVIEW name text box.
Direction Indicates whether the signal receives data from the CLIP or sends data to the CLIP.
Signal Type Displays the type of signal. You can change the signal type by selecting a new type in the Signal type pull-down menu.
Default LabVIEW Data Type Displays the default LabVIEW data type. You can change the data type in the Default LabVIEW Data Type section of this dialog box.
LabVIEW name Specifies a name corresponding to the HDL signal.
Signal type Specifies the type of signal for the signal you select in the table.You can select from the following values:
  • data—Use if the signal is a standard I/O data signal. If you do not specify a value for the SignalType tag, the default is data.
  • clock—Use if the signal is a clock. If you use clock, you must use the <Boolean/> tag within the DataType tag.
  • reset—Use if the signal is a reset signal that connects to the global asynchronous reset signal of the FPGA VI. The global asynchronous reset signal for FPGA VIs is active-high. You can use reset only if the InterfaceType tag is set to Fabric. A reset signal must be a ToCLIP signal.
  • clock status—There are two types of clock status signals: SourceClockReady and DerivedClocksValid. Both signals are required for each FromCLIP clock with the SupportDerivedClocks tag. These signals together implement the handshaking interface with the LabVIEW FPGA clocking circuitry that produces derived clocks.
terminal type selector Defines the data type of the signal. If the signal is for a LabVIEW interface, the data type also defines how LabVIEW represents this signal.
  • Fixed-point encoding—Specifies whether the selected terminal is Signed or Unsigned. This option is valid for fixed-point terminals only.
  • Integer word length—Specifies the integer word length of the selected terminal between [–2048, 2047]. This option is valid for fixed-point terminals only. LabVIEW sets the word length of the terminal to the width of the corresponding port as specified in the IP.
Signal description Specifies the description of the signal.