Advanced Code Generation Page (FPGA I/O Properties Dialog Box)

Select Advanced Code Generation in the Category list of the FPGA I/O Properties dialog box to display this page.

Use this page to select code generation options, such as arbitration and the number of synchronizing registers. You also can specify certain I/O options in the FPGA I/O Node Properties dialog box. Supported options, values, and defaults vary according to FPGA target and FPGA I/O. This page displays only the options and values supported by the selected FPGA I/O. Some FPGA targets might not allow access to this page at all.

This page can contain the following options:

Option Description
ArbitrationForInputData Specifies the type of arbitration the resource uses for input data. This option typically applies to FPGA I/O items where input requires multiple clock cycles.This option can include Always Arbitrate, Arbitrate if Multiple Requestors Only, and Never Arbitrate.
ArbitrationForOutputData Specifies the type of arbitration the resource uses for output data.This option can include Always Arbitrate, Arbitrate if Multiple Requestors Only, and Never Arbitrate.
ArbitrationForOutputEnable Specifies the type of arbitration the resource uses for output enable.This option appears for FPGA I/O with output enable, such as bidirectional digital I/O. This option can include Always Arbitrate, Arbitrate if Multiple Requestors Only, and Never Arbitrate.
NumberOfSyncRegistersForOutputData Specifies the number of synchronizing registers between the FPGA I/O function executing on the FPGA target and the FPGA target hardware interface. The FPGA target hardware interface might be a physical I/O connector on the device or a connection to a section of the FPGA that contains circuitry designed by NI.
Note To ensure consistent timing, use the same number of synchronization registers for output data and output enable.
Each synchronization register executes in one clock cycle.
Caution Select 0 only if you also use component-level IP (CLIP) and the HDL code contains its own synchronization registers.
Supported options typically include the following:

  • 0—Specifies that the FPGA VI uses no synchronization registers. Do not select this option for most FPGA Module applications.

    Note If you select 0 for digital input and digital output resources in a single-cycle Timed Loop, you create a combinatorial circuit between the two resources. The combinatorial circuit might cause glitches on the output signal.
  • 1—Specifies that the FPGA VI uses one synchronizing register between the FPGA I/O resource and the FPGA target hardware interface.
NumberOfSyncRegistersForOutputEnable Specifies the number of synchronizing registers between the FPGA I/O Node executing on the FPGA target and the FPGA target hardware interface.
Note To ensure consistent timing, use the same number of synchronization registers for output data and output enable.

This option appears for FPGA I/O with the Set Output Enable method available, such as bidirectional digital I/O.

Each synchronization register executes in one clock cycle.
Caution Select 0 only if you also use component-level IP (CLIP) and the HDL code contains its own synchronization registers.
Supported options typically include the following:

  • 0—Specifies that the FPGA VI uses no synchronization registers. Do not select this option for most FPGA Module applications.

    Note If you select 0 for digital input and digital output resources in a single-cycle Timed Loop, you create a combinatorial circuit between the two resources. The combinatorial circuit might cause glitches on the output signal.
  • 1—Specifies that the FPGA VI uses one synchronizing register between the FPGA I/O resource and the FPGA target hardware interface.
NumberOfSyncRegistersForRead Specifies the number of synchronizing registers between the FPGA target hardware interface and the FPGA I/O executing on the FPGA target. The FPGA target hardware interface might be a physical I/O connector on the device or a connection to a section of the FPGA that contains circuitry designed by NI.
Each synchronizing register executes in one clock cycle. If you use the FPGA I/O item outside a single-cycle Timed Loop, LabVIEW places one additional synchronizing register, or holding register, that attempts to hold the digital value constant for subsequent operations in the FPGA VI. These synchronizing registers are in addition to enable chain registers that are present outside of the single-cycle Timed Loop. If you use the FPGA I/O item inside a single-cycle Timed Loop, LabVIEW does not add the additional register because logic inside a single-cycle Timed Loop executes every clock cycle. However, you must use caution when synchronizing I/O in single-cycle Timed Loops.
Caution Select 0 only if you also use component-level IP (CLIP) and the HDL code contains its own synchronization registers. Otherwise, you might introduce metastable data in the FPGA VI and experience unpredictable behavior.
Supported options typically include the following:

  • Auto—Specifies that LabVIEW uses the default number of synchronizing registers between the FPGA hardware I/O interface and the FPGA I/O Node implemented on the FPGA. The following table lists the number of registers LabVIEW uses depending on the location of the FPGA I/O Node on the block diagram.

    Location Synchronizing Registers Enable Chain Register
    Inside an SCTL 2 0
    Outside an SCTL 1 1

  • 0—Specifies that LabVIEW does not place any synchronizing registers between the FPGA hardware I/O interface and the FPGA I/O Node implemented on the FPGA. Do not select this option for most FPGA Module applications.

    Note If you select 0 for digital input and digital output resources in a single-cycle Timed Loop, you create a combinatorial circuit between the two resources. The combinatorial circuit might cause glitches on the output signal.
    The following table lists the total number of registers LabVIEW uses depending on the location of the FPGA I/O Node on the block diagram.
    Location Synchronizing Registers Enable Chain Register
    Inside an SCTL 0 0
    Outside an SCTL 1 1

  • 1—Specifies that LabVIEW place one synchronizing registers between the FPGA hardware I/O interface and the FPGA I/O Node implemented on the FPGA.

    Note You might encounter metastable data if the FPGA I/O Node is in a single-cycle Timed Loop and set with this option when the data is not already synchronized to the clock of the single-cycle Timed Loop.
    The following table lists the total number of registers LabVIEW uses depending on the location of the FPGA I/O Node on the block diagram.
    Location Synchronizing Registers Enable Chain Register
    Inside an SCTL 1 0
    Outside an SCTL 2 1

  • 2—Specifies that LabVIEW place two synchronizing registers between the FPGA hardware I/O interface and the FPGA I/O Node implemented on the FPGA. Select this option to avoid metastability if the value of the input to the FPGA I/O Node read element might change while the FPGA I/O Node samples the FPGA target hardware interface. If you select this option for an FPGA I/O Node within a single-cycle Timed Loop, you have no metastable data in the FPGA VI. The following table lists the total number of registers LabVIEW uses depending on the location of the FPGA I/O Node on the block diagram.

    Location Synchronizing Registers Enable Chain Register
    Inside an SCTL 2 0
    Outside an SCTL 3 1
Note Use the Advanced Code Generation FPGA I/O Node Properties page to specify the number of synchronization registers for digital input.