The top-level synthesis file defines the entity that the IP Integration Node synthesizes. If the top-level file is a .vhd file, this file also defines the architecture to use. In addition, the top-level synthesis file contains a list of ports that correspond to input and output terminals of the node.

LabVIEW assumes the first .vhd file, Xilinx IP configuration file, or netlist file you add is the top-level file. Complete the following steps to specify another file as the top-level synthesis file.

1. Ensure the file meets the requirements for top-level synthesis files.
2. If you have not done so already, add the synthesis file to the list of synthesis files the IP Integration Node uses.
3. Select this file in the IP Source table.
4. Click the Set as Top Level button:

   

   LabVIEW displays an icon to the left of the top-level file.