Use the IP Integration Node to integrate third-party IP into the block diagram of an FPGA VI. Using this node involves the following tasks.

1. Install the necessary Xilinx compilation tools on the computer you plan to use to configure the IP Integration Node.
2. Create or acquire IP synthesis files, such as .vhd files, Xilinx IP configuration files, or netlist files. Ensure the IP meets the requirements of the node.
3. If you plan to export the IP for simulation, create or acquire the files that define a simulation model.
4. Add the IP Integration Node to the block diagram.
5. Double-click the node to configure it. LabVIEW displays a configuration wizard you use to complete the following tasks.
   1. Define the name of the IP and the synthesis files that compose the IP, including the top-level synthesis file.
   2. Set the simulation behavior of each synthesis file. The combined behavior results in a simulation model for the node.
   3. If the top-level synthesis file is a .vhd file, define the top-level entity and architecture.
   4. Specify the FPGA families on which the IP can run.
   5. If the top-level synthesis file is a .vhd file, set the value of any generics and ensure their syntax is valid.
   6. Generate the simulation model.
   7. Specify any IP ports that correspond to clock enable signals.
   8. Specify any IP ports that correspond to synchronous or asynchronous reset signals.
   9. Specify when and how the IP resets.
   10. Define the block diagram terminals that appear and set the data types of these terminals.

After you complete these steps, LabVIEW generates the code to integrate the IP into the FPGA VI.

IP Integration Node Properties Wizard

Use the IP Integration Node Properties wizard to configure the IP Integration Node.

The IP Integration Node Properties wizard contains the following pages:

1. Name and Source
2. Entity, Architecture, and Targets
3. Generics and Support File Generation
4. Clock and Enable Signals
5. Reset Signals and Behavior
6. IP Terminals