Even if you do not plan to export the FPGA VI for simulation, you must generate support files before you can completely configure and use the IP Integration Node. Complete the following steps to generate support files.

1. On the Name and Source page of the IP Integration Node configuration wizard, ensure each synthesis file has the simulation behavior you want.
2. Navigate to the Generics and Support File Generation page.
3. (Optional) If the top-level synthesis file is a .vhd file that contains VHDL generics, set the values of these generics as appropriate. Use the Check Syntax button to ensure the syntax you enter is valid.
4. (Optional) To regenerate the entire simulation model, remove the checkmark from the Regenerate out-of-date support files only checkbox. Otherwise, LabVIEW generates only the synthesis components that have changed since the last time you generated the simulation model.
5. Click the Generate button to generate the support file.