Integrating Third-Party IP

You can use two methods to integrate third-party IP into FPGA VIs: the component-level IP (CLIP) interface and the IP Integration Node. This topic compares each method to help you decide which works better for your FPGA application.

Supported IP File Types

You can use third-party IP defined using:

  • VHDL
  • Verilog
  • Netlist files
  • Xilinx IP configuration files: (Xilinx ISE) .xco files or (Xilinx Vivado) .xci files

Refer to the CLIP Interface and IP Integration Node Details section for more information about supported file types for the CLIP interface and the IP Integration Node.

Note To import Verilog files or a large file hierarchy, you first need to compile this IP to a netlist file.

Xilinx IP

Xilinx provides and maintains the Xilinx IP. LabVIEW uses the IP Integration Node to incorporate Xilinx IP into an FPGA VI. Because Xilinx may deprecate IP cores from older releases, NI only can guarantee support in the IP Integration Node for Xilinx IP configuration files created using the current version of the Xilinx compilation tools for your FPGA target. Refer to the support document at ni.com for more information about NI hardware supported by each Xilinx compilation tool.

Note Xilinx licenses the Xilinx IP. You can find the licensing information in the Context Help window for a specific Xilinx IP. To import a license, place the .lic file in one of the following default directories, depending on your specific FPGA target:
  • (Xilinx ISE) C:\NIFPGA\programs\XilinxY_Z\ISE\coregen\core_licenses, where XilinxY_Z is the current version of the Xilinx compilation tool for ISE for your FPGA target.
  • (Xilinx Vivado) C:\NIFPGA\programs\VivadoA_B\data\ip\core_licenses, where VivadoA_B is the current version of the Xilinx compilation tool for Vivado for your FPGA target.

(Xilinx ISE) NI installs the Xilinx IP generator, coregen.exe, in the same directory as LabVIEW.exe. By default, the Xilinx IP generator is located in the C:\NIFPGA\programs\XilinxY_Z\ISE\bin\nt directory, where XilinxY_Z is the current version of the Xilinx compilation tool for ISE for your FPGA target.

If you migrate Xilinx IP from one FPGA target to another or from one version of LabVIEW to another, you may have to regenerate the IP on the new target.

CLIP Interface and IP Integration Node Details

The following table compares the two methods of integrating third-party IP in more detail.

Note Top-level VHDL files support only the std_logic and std_logic_vector port types.