The LabVIEW FPGA Module is ideal for programming applications that require functionality such as the following:

• Custom I/O—You can modify digital and analog lines with custom counters, encoders, and pulse width modulators (PWMs).
• Onboard decision making—You can make control, digital filtering, and Boolean decisions on the target.
• Resource synchronization—Applications run with the precise timing of FPGA target resources, such as analog input (AI), analog output (AO), digital input and output (DIO), counters, and PWMs. You also can synchronize applications among multiple FPGA targets.
• Parallel execution—Independent portions of the block diagram can execute in parallel on the FPGA. For example, multiple independent While Loops on a block diagram each run simultaneously on independent portions of the FPGA. Adding additional independent loops does not affect the performance of existing loops.
• Independent and deterministic execution—FPGA VIs continue to run even if the computer that controls and monitors the FPGA target crashes.

Programming FPGAs with LabVIEW

The following outline provides an overview of steps involved for programming your FPGA target. The list is not a complete set of instructions. The LabVIEW Documentation includes topics to help you with the specifics of developing FPGA applications.

1. Understand the hardware capabilities of your target—Refer to the specific FPGA target or chassis hardware documentation for information about the capabilities and functionality of your FPGA and target.
2. Create an FPGA project for your application—You must create a LabVIEW project with an FPGA target before you can begin developing FPGA applications.
3. Create the FPGA VI—You can create FPGA VIs from scratch or get started with an example VI. Use the NI Example Finder to find example VIs for your target.
4. (Optional) Create a host VI—Host VIs run on an RT target or a PC and control and monitor FPGA VIs.
5. Compile and download the FPGA VI to the target—You must compile the FPGA VI before you can download and run it on an FPGA target.