You can use the IP Integration Node to integrate IP that is designed to execute faster than the single-cycle Timed Loop that contains the node. In this situation, the IP must use an FPGA-derived clock that executes at a rate that is an integer multiple of the clock signal you wire to the single-cycle Timed Loop. For example, if a single-cycle Timed Loop clock runs at 100 MHz, you can integrate IP that runs at 100 MHz, 200 MHz, 300 MHz, 400 MHz, and so on.

Complete the following steps to configure the IP Integration Node to execute faster than the containing single-cycle Timed Loop.

1. Ensure your IP synchronizes its output ports to the rising edge of the single-cycle Timed Loop clock.
2. Create the FPGA-derived clock and set it to the rate the IP requires. The FPGA-derived clock appears as an item in the Project Explorer window.
   Note The FPGA-derived clock must be phase-aligned to the single-cycle Timed Loop clock. The Message field in the FPGA Derived Clock Properties dialog box displays a warning if phase alignment is not possible. Phase alignment is not possible when the frequency of the single-cycle Timed Loop clock is outside the supported frequency range for phase alignment.
3. Double-click the IP Integration Node and navigate to the Clock and Enable Signals page.
4. In the Derived Multiple of Timed Loop Clock pull-down menu, specify the port in the IP that corresponds to the FPGA-derived clock.
5. Specify the Relative clock rate of the derived clock. For example, if the base clock executes at 100 MHz and the FPGA-derived clock executes at 400 MHz, enter 4x.
6. If the FPGA-derived clock has an enable signal, specify this signal in the IP Enable Signal(s) list.
7. Click the Next button and the Finish button until you return to the block diagram.
8. Add an FPGA clock constant to the block diagram and select the FPGA-derived clock you created.
9. Wire the output of this constant to the derived clock input of the IP Integration Node.

The IP Integration Node now executes faster than the SCTL that contains the node.