Optimizing FPGA VIs for Speed and Size

If you want to optimize the performance of an FPGA VI, you might be able to modify the FPGA VI to increase speed, decrease the FPGA logic utilization, or both.

The following table includes techniques you can use to optimize an FPGA VI.

Note To understand the techniques in this table, you must be familiar with registers.
Optimization Technique FPGA Speed FPGA Size

Reduce combinatorial paths.

1378

Use pipelining when appropriate.

1378

Use single-cycle Timed Loops.

1378

1378

Use parallel operations.

1378

Select Never Arbitrate as an arbitration option.

1378

1378

Use non-reentrant subVIs.

1378

Use reentrant subVIs.

1378

Limit the number of front panel objects, such as arrays.

1378

Use the smallest data type possible.

1378

1378

Limit the size of custom data types.

1378

1378

Avoid large VIs and functions, if possible.

1378

1378

Schedule timing using handshaking signals.

1378

1378

Use an external data value reference when accessing DMA FIFOs.

1378

1378

Reduce block memory resource usage by configuring dual port read access if possible.

1378

1378

Choose a block memory implementation for array constants unless you need the advantages of a different type of memory. Block memory does not consume FPGA resources and tends to compile at a high clock rate relative to other types of memory.

1378

1378

Remove the implicit enable signal from single-cycle Timed Loops that run independently of other nodes on the block diagram. This strategy is most useful for very large designs.

1378