Optimizing FPGA VIs for Speed and Size
- Updated2023-12-13
- 4 minute(s) read
Optimizing FPGA VIs for Speed and Size
If you want to optimize the performance of an FPGA VI, you might be able to modify the FPGA VI to increase speed, decrease the FPGA logic utilization, or both.
The following table includes techniques you can use to optimize an FPGA VI.
Optimization Technique | FPGA Speed | FPGA Size |
Reduce combinatorial paths. |
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Use pipelining when appropriate. |
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Use single-cycle Timed Loops. |
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Use parallel operations. |
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Select Never Arbitrate as an arbitration option. |
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Use non-reentrant subVIs. |
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Use reentrant subVIs. |
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Limit the number of front panel objects, such as arrays. |
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Use the smallest data type possible. |
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Limit the size of custom data types. |
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Avoid large VIs and functions, if possible. |
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Schedule timing using handshaking signals. |
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Use an external data value reference when accessing DMA FIFOs. |
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Reduce block memory resource usage by configuring dual port read access if possible. |
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Choose a block memory implementation for array constants unless you need the advantages of a different type of memory. Block memory does not consume FPGA resources and tends to compile at a high clock rate relative to other types of memory. |
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Remove the implicit enable signal from single-cycle Timed Loops that run independently of other nodes on the block diagram. This strategy is most useful for very large designs. |
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Related Information
- Managing Shared Resources
- Introduction to FPGA Hardware Concepts
- Reducing Combinatorial Paths in FPGA VIs
- Optimizing FPGA VIs Using Pipelining
- Using Single-Cycle Timed Loops to Optimize FPGA VIs
- Using Parallel Operations
- Avoiding Arbitration to Optimize FPGA VIs
- Determining When to Use Reentrant or Non-Reentrant SubVIs
- Limiting the Number of Top-Level Front Panel Objects in FPGA VIs
- Using the Smallest Data Type to Optimize FPGA VIs
- Using Custom Data Types with Register Items, Memory Items, FIFOs, and Handshake Items
- Avoiding Large VIs and Functions in FPGA VIs When Possible
- Scheduling Timing Using Handshaking Signals
- Reducing Memory Resource Usage with Dual-Port Read Access