Excluding a Synthesis File from Simulation

If you do not need to simulate a synthesis file, or if another simulation model already includes the simulation model of a synthesis file, you can exclude that file from simulation. Excluding a file reduces the chance of errors occurring during simulation.

Note   Even if you do not plan to export an FPGA VI for simulation, you cannot exclude the top-level synthesis file from simulation.

Complete the following steps to exclude a synthesis file from simulation.

  1. Select one or more synthesis files in the IP Source table.
  2. Click the Set Simulation Behavior button:

    LabVIEW displays the Set Simulation Behavior dialog box.
  3. Select the Exclude from simulation model option:

  4. Click the OK button to return to the configuration wizard.