Controlling I/O Power-On States
- Updated2023-12-13
- 2 minute(s) read
Controlling I/O Power-On States
An application might require that the I/O on the FPGA target be set to a known value when the system powers on. For example, if an FPGA target controls hydraulic valves with the digital outputs, the FPGA target must keep the valves turned off until the host VI is launched and starts to control the system. You can create an FPGA VI and configure the FPGA target to set the power-on states of the FPGA target.
You must program the FPGA VI so that the block diagram sets the output states without any dependencies on the host VI. For example, you can place the digital and analog output functions in the first frame of a sequence structure. You then place the rest of the LabVIEW code in the subsequent frames of the sequence structure, as shown in the following block diagram. Then configure the FPGA VI to start executing as soon as it is loaded in the FPGA. Compile and download the FPGA VI to the flash memory on the FPGA target and configure the FPGA target to automatically load the FPGA VI from the flash memory when the FPGA target powers on. When the FPGA target powers on, the FPGA VI loads into the FPGA from the flash memory, and the FPGA VI starts executing immediately. The output functions in the first frame of the sequence structure on the FPGA VI set the power-on output states.
You can create more than a static power-on state for the outputs of the FPGA target. You can create arbitrary power-on functionality that performs complex actions. For example, you can set outputs based on the state of the inputs, use serial communication with an external device, and so on. Refer to the specific FPGA target hardware documentation for information about default power-on states.