Using the Fixed-Point Data Type
- Updated2023-12-13
- 3 minute(s) read
Using the Fixed-Point Data Type
The fixed-point data type provides some of the flexibility of the floating-point data type, but maintains the size and speed advantages of integer arithmetic. Refer to ni.com for more information about the fixed-point data type and working with this data type.
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Caution If you wire a fixed-point number to an integer terminal, you might lose fractional bits. |
Fixed-Point Configuration Effects on FPGA Resources
When using fixed-point numbers in an FPGA VI, it is important to select the proper overflow and rounding modes for a particular function. The High Throughput Math functions and some Numeric functions have configuration dialog boxes you use to select these modes. If overflow or rounding can occur, these modes affect the amount of FPGA resources an FPGA VI needs. If overflow or rounding cannot occur, the operation does not require additional FPGA resources.
In many situations, you can avoid overflow by placing a checkmark in the Adapt to source checkbox in the configuration dialog box of the function. If you place a checkmark in this checkbox, LabVIEW attempts to adjust the width and range of the output data type such that neither overflow nor rounding occurs. However, this adjustment is not possible in all situations. For example, if a function involves division, rounding always occurs. Also, some functions do not have this checkbox.
Effects of Overflow Modes
In general, the overflow modes affect FPGA resource usage in the following ways:
- Saturate—Requires FPGA resources to determine whether the input value is within the range of the output type and to choose whether to return the original or saturated value.
- Wrap—Requires fewer FPGA resources than the Saturate mode.
Effects of Rounding Modes
In general, the rounding modes affect FPGA resource usage in the following ways:
- Truncate—Removes bits and therefore does not require any FPGA resources. However, this mode produces the largest mean error for most data streams. This mode is the default for integer operations.
- Round-Half-Up (Asymmetric)—Adds to the least significant bit of the output data type. This option requires an adder that is the width of the output data type.
- Round-Half-Even—Requires the most FPGA resources and results in the longest combinatorial path of the three rounding modes. However, this mode returns the most statistically correct results for most data streams and is therefore the default rounding mode for the fixed-point data type.