To transfer data between different portions of an FPGA VI, between VIs on an FPGA target, or between devices, use a FIFO. A FIFO is a data structure that holds elements in the order they are received and provides access to those elements using a first-in, first-out access policy.

The following illustration demonstrates the behavior of elements moving through a FIFO.

Use FIFOs to transfer data in the following ways:

• Between parallel loops within one clock domain
• Across clock domains
• Between peer-to-peer targets
• Between the host computer and the FPGA

Use the FIFO Properties dialog box to create and configure FIFOs.

All FIFOs except VI-defined FIFOs have a corresponding item in the project. Therefore, if you use a FIFO other than a VI-defined FIFO and send the FPGA VI to another user, you must send the entire project. Otherwise, you cannot run the FPGA VI.

Use the following flow chart to determine the FIFO configuration that best fits your application needs.

The following figure shows an example of a target-scoped FIFO used to transfer data between two single-cycle Timed Loops in the same FPGA VI. The single-cycle Timed Loops are in two different clock domains. The top loop uses an 80 MHz clock and the bottom loop uses a 40 MHz clock. In this example, an FPGA I/O Node in the 80 MHz clock domain acquires temperature readings from a device. A FIFO Method node writes the data to a FIFO. If the empty elements in the FIFO are not available for writing immediately, the node times out, stops the loop, and sets the Write Timed Out? indicator to TRUE. A FIFO Method node in the 40 MHz clock domain reads the data, then passes the data to a Less Than 0? function. If the temperature is less than zero, the function sets the Device Frozen? indicator to TRUE. If the data is not available to read immediately, the FIFO Method node times out, stops the loop, and sets the Read Timed Out? indicator to TRUE.

Data Transfer Tasks

You can transfer data in the following ways:

• Within one FPGA target—Use these types of FIFOs to transfer data between VIs, to and from loops in a single VI, or between clock domains.
  • Target-scoped FIFOs—Use target-scoped FIFOs if you want the FIFO to be visible and configurable from the Project Explorer window. Target-scoped FIFOs have a corresponding item in the project. Updates to the project item affect all instances of the FIFO. Target-scoped FIFOs are accessible within any VI under the same FPGA target in the Project Explorer window. If you use a target-scoped FIFO and want to send the FPGA VI to another user, you have to send the entire project. Otherwise, the FPGA VI is broken.
  • VI-defined FIFOs— Use VI–defined FIFOs along with FIFO name controls to create reentrant subVIs and avoid resource conflicts. If you configure a VI-defined FIFO in a reentrant FPGA VI, LabVIEW creates a separate copy of the FIFO for each instance of the VI.
• Between the host and the FPGA—Use direct memory access (DMA) FIFOs to transfer large amounts of data between the host and the FPGA. This type of FIFO directly accesses memory to transfer data from FPGA target VIs to host VIs and vice versa. A DMA FIFO allocates memory on both the host computer and the FPGA target, yet acts as a single FIFO. DMA FIFOs provide performance advantages over using front panel controls and indicators to communicate between the host and the FPGA.
• Between two peer-to-peer targets—Use peer-to-peer FIFOs to transfer data between peer-to-peer targets without sending the data through the host. You can use peer-to-peer streaming to send data between FPGA and non-FPGA targets, but the targets must be capable of using the peer-to-peer stream architecture. Peer-to-peer FIFOs have a corresponding item in the project.