DSP48E Example: Creating a Complex Multiplier

You can use four DSP48E slices to implement a complex multiplier. The inputs to this multiplier are four fixed-point numbers (x1, x2, y1, and y2), each pair of which represents a complex number:

  • x1 + j * y1
  • x2 + j * y2

The complex multiplier takes these inputs and produces two fixed-point numbers:

  • x1 * x2 – y1 * y2
  • x1 * y2 + x2 * y1

You then can calculate (x1 * x2 – y1* y2) + j(x1 * y2 + x2 * y1).

Complete the following steps to create a complex multiplier.

  1. Create a new, blank VI on a supported FPGA target.
  2. Add a DSP48E function to the block diagram.
  3. Double-click this function and configure it in the following ways:
    1. Function page:

    2. Terminals page:

    3. Click the OK button to save changes and return to the block diagram.
    This function is now Function 0.
  4. Press the <Ctrl> key and drag the function below the current one. This action creates a copy of the DSP48E function, Function 1. The copy has the same configuration as the original. The block diagram now resembles the following figure:

  5. Add another DSP48E function to the right of Function 0. This new function will be Function 2.
  6. Double-click this function and configure it in the following ways:
    1. Function page:

    2. Terminals page:

    3. Registers page:

      Adding an extra register to each data path ensures the latencies are balanced in this application.
    4. Click the OK button to save changes and return to the block diagram.
  7. Press the <Ctrl> key and drag this function to the right of Function 1, below Function 2.
  8. Double-click this new copy and configure the Function page in the following way:

  9. Click the OK button to save changes and return to the block diagram, which now resembles the following figure:

  10. Create and wire the controls and indicators as shown in the following figure:

    Note   Depending on the sources of data for x1, x2, y1, and y2, you might need to configure the integer word lengths of the DSP48E input terminals.
  11. Save the VI to a convenient location as DSP48E Complex Multiplier.vi.

You now can export this VI for simulation. To run this VI on an FPGA target, you must enclose the code in a single-cycle Timed Loop.

Tip You can shrink the functions' icons to save space on the block diagram.