You can read each report in the Compilation Status window after the report becomes available during the compilation of the FPGA VI. Use the information in the reports to determine whether the FPGA VI fits on the FPGA and meets timing constraints. The reports available in the Compilation Status window vary depending on your specific FPGA target.

Summary Report Details

This report contains a summary of the generated bitfile and is available only when the compilation is complete. If the report contains timing errors, you can investigate the errors by clicking the Timing Violation Analysis button.

Configuration Report Details

This report displays project information and the Xilinx compiler configuration you specified in the Xilinx Options page of the build specification.

Estimated Device Utilization (Pre-Synthesis) Report Details

This report is available after LabVIEW estimates FPGA resource usage using the Xilinx tools. The availability of this report depends on your specific FPGA target. This report includes the following information:

• Device Utilization—Indicates the FPGA element, such as slices, flip-flops, LUTs, and blocks of RAM.
• Used—Indicates how many of the FPGA element the compiled FPGA VI uses.
• Total—Indicates the total number of FPGA elements in the FPGA.
• Percent—Indicates the percentage of the FPGA elements that the FPGA application uses. If Percent is greater than 100, a warning message alerts you that the estimated device utilization exceeds 100 percent. Depending on the FPGA VI and hardware, Xilinx still may be able to fit everything on the FPGA. However, you may want to optimize the FPGA VI.

Estimated Device Utilization Report Details

This report is available after the compile server completes the synthesizing step of the compilation process. This report contains a summary of the FPGA utilization as estimated during the synthesis of the FPGA VI. This report includes the following information:

• Device Utilization—Indicates the FPGA element, such as slices, flip-flops, LUTs, and blocks of RAM.
• Used—Indicates how many of the FPGA element the compiled FPGA VI uses.
• Total—Indicates the total number of FPGA elements in the FPGA.
• Percent—Indicates the percentage of the FPGA elements that the FPGA application uses. If Percent is greater than 100, a warning message alerts you that the estimated device utilization exceeds 100 percent. Depending on the FPGA VI and hardware, Xilinx still may be able to fit everything on the FPGA. However, you may want to stop the compilation and optimize the FPGA VI.

Final Device Utilization Report Details

This report is available after the compile server completes the mapping or placement step of the compilation process. This report contains a summary of the FPGA utilization, including the following information:

• Device Utilization—Indicates the FPGA element, such as slices, flip-flops, LUTs, and blocks of RAM.
• Used—Indicates how many of the FPGA element the compiled FPGA VI uses.
• Total—Indicates the total number of FPGA elements in the FPGA.
• Percent—Indicates the percentage of the FPGA elements that the FPGA application uses. If Percent is greater than 100, the compilation failed. You must optimize the FPGA VI for size.

Estimated Timing Report Details

This report is available after the compile server completes the mapping or placement step of the compilation process. This report contains a summary of the FPGA clocks, as estimated during the mapping or placement of the FPGA VI. This report includes the following information:

• Clocks—Indicates the FPGA clocks.
• Requested (MHz)—Indicates the clock rate, in megahertz, at which the FPGA VI or FPGA VI component must be able to run. Some FPGA VI components, such as Timed Loops, are visible on the block diagram, while others, such as CLIP, are not. If Requested (MHz) is greater than Maximum (MHz), a warning message alerts you that the VI does not meet timing constraints. Depending on the FPGA VI and hardware, Xilinx may still be able to compile the FPGA VI such that it meets timing constraints. However, you may want to stop the compilation and optimize the FPGA VI.
• Maximum (MHz)—Indicates the theoretical maximum compilation rate, in megahertz, for the FPGA VI or FPGA VI component.

Final Timing Report Details

This report is available after the compile server completes the routing step of the compilation process. This report contains a summary of the FPGA clocks, including the following information:

• Clocks—Indicates the FPGA clocks.
• Requested (MHz)—Indicates the clock rate, in megahertz, at which the FPGA VI or FPGA VI component must be able to run. Some FPGA VI components, such as Timed Loops, are visible on the block diagram, while others, such as CLIP, are not. If Requested (MHz) is greater than Maximum (MHz), the compilation fails. Click the Investigate Timing Violation button to analyze the timing violations.
• Maximum (MHz)—Indicates the theoretical maximum compilation rate, in megahertz, for the FPGA VI or FPGA VI component. For specific FPGA targets, the Xilinx compiler does not attempt to optimize if a design meets timing requirements.

Xilinx Log Report Details

This log file is available only after the compilation is complete. If you are familiar with Xilinx tools, you might be able to use this file to troubleshoot compilation failures. Click the Save button to save this information to a file.