Avoiding Buffer Errors in DMA Applications

The number of elements a DMA buffer can hold, also known as the size or depth of the buffer, is a critical part of designing a robust application. The number of elements in a buffer has the following effects on an application:

  • If the buffer is too small, the buffer fills up before data can be read and removed. In this situation, called an overflow, any data you write to the buffer is lost
  • If the buffer is too large, it uses an unnecessary number of resources on the FPGA and/or host computer, which can reduce the performance of the application
  • If you attempt to read more elements from a buffer than what is available, an underflow occurs and LabVIEW returns an error

To design a robust application, NI recommends that you:

  • Set the sizes of each buffer appropriately
  • Design the application to detect and avoid buffer overflows
  • Design the application to detect and avoid buffer underflows
  • Design the application to prevent stale data from accumulating in the buffers

The following sections provide more information about these strategies.

Setting Buffer Sizes Appropriately

The following table describes the two buffers that comprise a DMA channel, where to configure the size of each buffer, the recommended size of each buffer, and the maximum size of each buffer.

Location of Buffer Where to Configure Default Buffer Size Recommended Buffer Size Maximum Buffer Size
FPGA target General page of the FIFO Properties dialog box 1023 elements 1023 elements. For most applications, you do not need to change the size of the FPGA buffer. Depends on the amount of resources available on the FPGA and bytes allocated in memory on the host computer. If the FPGA does not have enough resources for the number of elements you specify, the FPGA VI fails to compile. Refer to the specific FPGA target hardware documentation for more information about DMA FIFO size limitations.
Host computer FIFO.Configure method of Invoke Method function 10,000 elements or twice the size of the FPGA FIFO buffer, whichever is greater Five times the number of elements you specify to read or write Depends on the amount of resources available on the FPGA and bytes allocated in memory on the host computer. If the FPGA does not have enough resources for the number of elements you specify, the FPGA VI fails to compile. Refer to the specific FPGA target hardware documentation for more information about DMA FIFO size limitations.

Detecting and Avoiding Buffer Overflows

To detect when a buffer might overflow, use the Get Number of Elements to Write method of the FIFO Method Node. This method returns the number of empty elements in the buffer to which you can write data. If this value is zero, the buffer is full; data you write to the buffer might be lost.

Use the following techniques to prevent buffer overflow:

  • Reduce the rate at which you write data to the buffer
  • Increase the Requested Number of Elements to read on the host
  • Increase the rate at which the host reads data
  • Increase the size of the host buffer, the FPGA buffer, or both
  • Reduce the load on the CPU on the host. The speed of the CPU and the presence of competing tasks reduce the transfer rate from the host buffer to application memory

Detecting and Avoiding Buffer Underflows

To detect when a buffer might underflow, use the Get Number of Elements to Read method of the FIFO Method Node. This method returns the number of elements in the buffer that are available to read. If this number is less than the number of elements you are reading from the buffer, reading from the buffer can cause the buffer to time out.

To detect when a buffer did underflow, check the FIFO.Read method for error –50400, as the following block diagram shows:

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You might want to take some action, such as stopping the application, if either problem occurs. You can use a Compound Arithmetic function configured as OR to stop execution of both the FPGA VI and the host VI when an overflow or underflow condition occurs.

Use the following techniques to avoid buffer underflow:

  • Increase the Timeout of the FIFO.Read method
  • Reduce the rate at which the host reads data
  • Reduce the number of elements the VI reads from the buffer by reducing the value of the Number of Elements control you wire to the FIFO.Read function

Preventing Stale Data from Accumulating in a Buffer

When you execute a VI on an FPGA target and stop and restart the VI, buffers do not reset, which means data remains in the buffers the next time you run the FPGA VI.

Use the following techniques to clear any buffers:

  • Reset the FPGA VI
  • Flush the buffer to read the remaining elements of the FIFO