Best Practices for DMA Applications

Consider the following best practices when working with DMA communication:

Best Practice Details
Refer to your FPGA target hardware documentation for information about how that target handles DMA transfers. DMA support and behavior varies by FPGA target. These differences have implications for how you design an application.
Set buffer sizes appropriately and check for overflows and underflows. The sizes of the DMA buffers have a large impact on the performance and robustness of your application.
Design your application to handle the following situations:
  • The Timed Out? indicator of the FIFO Method Node returns TRUE on FPGA targets.
  • The error out indicator of the FIFO Read Node returns code -50400 on RT targets.
 These situations indicate an error occurred in reading or writing data to or from one of the buffers. If you design your application to handle these situations instead of failing, your application will be more robust.
When using the FIFO.Write method to transfer data from the host computer to an FPGA target, always read the value of the Empty Elements Remaining indicator before attempting to write data to the buffer. The number of empty elements is guaranteed to be accurate for the next DMA operation. For most FPGA targets, this value is valid for subsequent operations also, decreasing by an amount equal to the size of each subsequent write. However, some FPGA targets recalculate this value after each write to the DMA channel. If you write to the channel in this situation, you risk LabVIEW discarding the data because the buffer might be full. The write operation also might time out.
When using the FIFO.Read method to read DMA data on the host computer, always read the value of the Elements Remaining indicator before attempting to read data from the buffer. Use a polling programming architecture where you read the number of elements remaining in the buffer before attempting to read data from the buffer.
Stop a FIFO before configuring its number of elements programmatically. If you configure the depth of a FIFO while the FIFO is running, the FIFO resets the next time it is started, which clears all data from the FIFO.
If you interleave multi-channel data, specify that the number of elements to write to the buffer is an integer multiple of the number of channels. This design ensures you can read the same amount of data from each channel. For example, if you have eight I/O channels and specify 80 in the Requested Number of Elements control in the FIFO Properties dialog box, the buffer has space for 10 samples from each channel.
On the host, read or write large amounts of data at a time. DMA communication incurs computational overhead; therefore, sending commands or small amounts of data wastes resources.