Every FPGA chip, or FPGA, is composed of a finite number of predefined resources with programmable interconnects. These interconnects implement the digital circuit you design with the LabVIEW FPGA Module. When you create an FPGA VI, you design a circuit schematic that describes how logic blocks are wired together on the FPGA. When you compile the VI, the compilation tools translate the FPGA VI into the FPGA circuit.

The following illustration shows the relationship between logic blocks, I/O blocks, and programmable routing on an FPGA.

The following FPGA specifications are important to consider when designing an FPGA application.

• Number of configurable logic blocks
• Number of fixed function logic blocks, such as multipliers
• Size of memory resources, such as embedded block RAM

Refer to the support document at ni.com for more information about the fundamental parts of the FPGA.

Flip-Flops, LUTs, and Slices

FPGA resources are resources on the FPGA that can perform logic functions. FPGA resources are grouped in slices to create configurable logic blocks. A slice contains a set number of LUTs, flip-flops and multiplexers. A LUT is a collection of logic gates hard-wired on the FPGA. LUTs store a predefined list of outputs for every combination of inputs and provide a fast way to retrieve the output of a logic operation. A flip-flop is a circuit capable of two stable states and represents a single bit. A multiplexer, also known as a mux, is a circuit that selects between two or more inputs and outputs the selected input.

Different FPGA families implement slices and LUTs differently. For example, a slice on a Virtex-II FPGA has two LUTs and two flip-flops but a slice on a Virtex-5 FPGA has four LUTs and four flip-flops. In addition, the number of inputs to a LUT, commonly two to six, depend on the FPGA family.

Registers

A register is a group of flip-flops that stores a bit pattern. A register on the FPGA has a clock, input data, output data, and enable signal port. Every clock cycle, the input data is latched, stored internally, and the output data is updated to match the internally stored data. FPGA VIs use registers to perform the following functions:

• Holding state between iterations of a loop
• I/O synchronization
• Handshaking data between clock domains
• Pipelining
• Communicating with a host VI

Registers are a key concept in understanding timing considerations for FPGA VIs.

Block RAM

Block RAM, or block memory, is RAM that is embedded throughout the FPGA for storing data. In general, LabVIEW uses block RAM when synthesizing Memory & FIFO functions. You can specify how LabVIEW implements FIFOs and memory items in the FIFO Properties and Memory Properties dialog boxes, respectively.

DSP48E and DSP48E1

A DSP48E slice is a digital signal processing logic element included on certain FPGA device families, such as the Xilinx Virtex-5. You can use this slice to perform different kinds of arithmetic operations, including a multiply-accumulator, multiply-adder, and a one- or n-step counter. You also can use the slice to perform different kinds of logic operations, such as AND, OR, and XOR. You can cascade multiple DSP48E slices to implement more complex functions, including complex multipliers and n-tap finite impulse response (FIR) filters, without using any additional FPGA fabric resources.

A DSP48E1 slice is a digital signal processing element available only on certain Xilinx Virtex-6 and newer FPGA device families. The DSP48E1 slice includes a pre-adder before the multiplier and other features that extend the functionality of a DSP48E slice. This pre-adder is useful in implementing certain algorithms, such as symmetric FIR filters.

UltraRAM

UltraRAM, or URAM, is a flexible, high-density, and large-size memory building block available on most Xilinx UltraScale+ targets. UltraRAM has eight times the capacity of a block memory but is less flexible in data width and address space configuration than block memory. Use UltraRAM as a storage element for large local FIFOs. You can specify how LabVIEW implements FIFOs in the FIFO Properties dialog box.