Signal and Trigger Routing

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FlexRIO devices with integrated I/O can send and receive signals through the front panel connectors and the PXI trigger bus. The front panel connectors provide connectivity for the input and output signals and for the control lines that send and receive clocks, triggers, and events. You can use the PXI trigger bus to send and receive events and triggers.

PXI Trigger Lines

FlexRIO devices with integrated I/O support sharing signals with other devices via the PXI trigger bus. Host software connects a logical device terminal to a specific PXI Trigger line or to a terminal on another device. An FPGA I/O Node can then read or write the logical signal from the FPGA diagram. FlexRIO devices with integrated I/O provide 32 logical sources (Source0 through Source31) that can drive signals on the PXI trigger bus, and 32 logical destinations (Destination0 through Destination31) that can receive signals from the PXI trigger bus. Use FPGA I/O nodes to write to and read from these sources and destinations. These logical sources and destinations are not connected to the PXI trigger bus until host software creates an appropriate route. You can create a route by using niFlexRIO_RouteSignal or by providing a terminal name as a routing property.

Terminal Names and Aliasing

A terminal name is a unique identifier that refers to a physical terminal in your system. To guarantee the uniqueness of a terminal name across multiple devices, terminal names begin with a forward slash, followed by the name of the device as configured in MAX, such as Dev1. A forward slash and the name of the terminal, such as PFI1, follow the device identifier. For example, the fully qualified terminal name for PFI1 on Dev1 is /Dev1/PFI1.

Each of the routing matrix's 32 Source signals and 32 Destination signals can be assigned an alias by renaming the I/O item in the LabVIEW FPGA Project. These aliases become valid terminal names once the bitfile has been opened on the device, and can be used wherever a terminal name is expected.