FlexRIO MGT DIO General Properties Page

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This socket connects the user diagram with the DIO MGTs, Reference Clocks, and support signals. Reference Clock IBUFGTs are already instantiated and should not be added in the CLIP.

This page includes the following components:

  • Socketed Component-Level IP Declaration—Specifies the socketed CLIP to use. Socketed CLIP allows your IP to communicate with both the FPGA VI and the I/O module connector interface.