FPGA Base Clock Resources for FlexRIO with Integrated I/O

A base clock is a digital signal existing in hardware that you can use as a clock for an FPGA application.

You can use the following base clock resources for FlexRIO with Integrated I/O devices:

80 MHz Clock

The 80 MHz Onboard Clock is the default clock in your LabVIEW FPGA project. This clock can be used as a top-level clock for running your LabVIEW FPGA VI. The top-level clock on an FPGA target determines the execution time of the individual functions and VIs on the FPGA VI block diagram. If you change the frequency of the top-level clock, you also change the execution speed of functions on the block diagram and the execution rate of the FPGA VI.

PXIe_Clk100

PXIe_Clk100 can be used as a source for running your LabVIEW FPGA VI.

300 MHz Clock

The 300 MHz Clock can be used as a source for running your LabVIEW FPGA VI. Refer to the FPGA Base Clock Properties Dialog Box topic of the LabVIEW FPGA Module Help for more information about configuring base clocks on your FPGA target.

DRAM Clock

The DRAM Clock drives the DRAM interface. Refer to the FPGA Base Clock Properties Dialog Box topic in the LabVIEW FPGA Module Help for more information about configuring base clocks on your FPGA target.
Note Some FlexRIO with Integrated I/O FPGA variants do not have onboard DRAM. The DRAM clock is only available on variants that include onboard DRAM.