FlexRIO Modular I/O FPGA Status Items
- Updated2025-01-23
- 8 minute(s) read
FlexRIO Modular I/O FPGA Status Items
You can use an FPGA I/O Node, configured for reading and writing, with the your FlexRIO Modular I/O FPGA Module. The FPGA I/O Node is located on the FPGA I/O Functions palette and performs specific FPGA I/O operations on your FPGA target.
The IO Module Status terminals are synchronous to the 40 MHz clock, and they should be accessed through that clock domain.
PXI-795x Status
Items
Board IO FPGA I/O Items
| FPGA I/O Item | Description |
|---|---|
| Device Temperature | Returns the current temperature of the device, in increments of
1 °C. The temperature is measured
from an onboard temperature sensor on the module PCB, external to
the FPGA. Note The
Device Temperature terminal is synchronous to the 40 MHz clock, and it should be
accessed through that clock domain. Note The Device
Temperature interface requires some time to fully initialize
after FPGA download and reset operations. When performing an
FPGA download or reset, wait at least 250 ms before reading the Device Temperature
terminal. |
| LEDs | Provides read/write access to the four onboard LEDs (reference designator D<2..5>, located on the module PCB). You can configure these LEDs any way that is useful to you during development and debugging. The four LEDs are accessed through bits <0..3> of the U8 data type. |
IO
Module Status FPGA I/O Items
| FPGA I/O Item | Description |
|---|---|
| EEPROM Power Enabled |
TRUE = Indicates that the adapter module EEPROM power rail is enabled. FALSE = Indicates that the adapter module EEPROM power rail is not enabled. |
| Expected IO Module ID | Reports the unique 32-bit IO Module ID that the currently downloaded FPGA VI is configured to use. The inserted IO Module ID must match the expected IO Module ID so the adapter module can function properly. The Expected IO Module ID is configured by choosing the appropriate adapter module in the IO Module General Properties dialog box and then recompiling and redownloading the FPGA VI. |
| Inserted IO Module ID | Reports the unique 32-bit IO module ID of the currently inserted adapter module. The Inserted IO Module ID must match the expected IO Module ID for the adapter module to function properly. |
| IO Module IO Enabled |
TRUE = Indicates that the adapter module connector FPGA I/O pins are enabled. FALSE = Indicates that the adapter module connector FPGA I/O pins are not enabled. Note These pins are
enabled only when an adapter module is connected, properly
powered, and when the FPGA has determined that the connected
adapter module is compatible with the FPGA VI currently
downloaded to the FPGA.
|
| IO Module Power Enabled |
TRUE = Indicates that the adapter module power is fully enabled. FALSE = Indicates that the adapter module power is not enabled. Note Adapter module
power is enabled only when an adapter module is connected and
the FPGA has determined that the connected adapter module is
compatible with the program currently downloaded to the
FPGA.
|
| IO Module Power Good | Reports the state of the power good signal on the adapter module
connector interface. TRUE = Indicates that the connected adapter module power rails have had the proper amount of time to initialize and are operational and stable. FALSE = Indicates that the connected adapter module power rails are not ready. |
| IO Module Present |
TRUE = Indicates that an adapter module is physically connected to the FPGA module. FALSE = Indicates that an adapter module is not connected to the FPGA module. |
PXIe-796x Status
Items
IO
Module Status FPGA I/O Items
| FPGA I/O Item | Description |
|---|---|
| EEPROM Power Enabled |
TRUE = Indicates that the adapter module EEPROM power rail is enabled. FALSE = Indicates that the adapter module EEPROM power rail is not enabled. |
| Expected IO Module ID | Reports the unique 32-bit IO Module ID that the currently downloaded FPGA VI is configured to use. The inserted IO Module ID must match the expected IO Module ID so the adapter module can function properly. The Expected IO Module ID is configured by choosing the appropriate adapter module in the IO Module General Properties dialog box and then recompiling and redownloading the FPGA VI. |
| Inserted IO Module ID | Reports the unique 32-bit IO module ID of the currently inserted adapter module. The Inserted IO Module ID must match the expected IO Module ID for the adapter module to function properly. |
| IO Module IO Enabled |
TRUE = Indicates that the adapter module connector FPGA I/O pins are enabled. FALSE = Indicates that the adapter module connector FPGA I/O pins are not enabled. Note These pins are
enabled only when an adapter module is connected, properly
powered, and when the FPGA has determined that the connected
adapter module is compatible with the FPGA VI currently
downloaded to the FPGA.
|
| IO Module Power Enabled |
TRUE = Indicates that the adapter module power is fully enabled. FALSE = Indicates that the adapter module power is not enabled. Note Adapter module
power is enabled only when an adapter module is connected and
the FPGA has determined that the connected adapter module is
compatible with the program currently downloaded to the
FPGA.
|
| IO Module Power Good | Reports the state of the power good signal on the adapter module connector interface. TRUE = Indicates that the connected adapter module power rails have had the proper amount of time to initialize and are operational and stable. FALSE = Indicates that the connected adapter module power rails are not ready. |
| IO Module Present | TRUE = Indicates that an adapter module is physically connected to the FPGA module. FALSE = Indicates that an adapter module is not connected to the FPGA module. |
Board IO FPGA I/O Items
| FPGA I/O Item | Description |
|---|---|
| Device Temperature | Returns the current temperature of the device, in increments of 1
°C. The temperature is measured from an onboard temperature sensor
on the module PCB, external to the FPGA. Note The Device
Temperature terminal is synchronous to the 40 MHz clock, and it
should be accessed through that clock domain. Note The Device
Temperature interface requires some time to fully initialize
after FPGA download and reset operations. When performing an
FPGA download or reset, wait at least 250 ms before reading the
Device Temperature terminal. |
| Clock100 PLL Unlocked | Indicates if the PLL that generates the 40 MHz, 100 MHz, and 200
MHz base clocks has unlocked after the FPGA bitfile download. After
the FPGA bitfile downloads, the PLL locks to PXIe_CLK100 by default.
If PXIe_CLK100 is not present, the PLL locks to an onboard 100 MHz
oscillator. If the PLL unlocks from PXIe_CLK100 (due to a glitch on
the clock, for example) the FPGA then attempts to relock the PLL to
the 100 MHz oscillator. Note NI recommends
that you reload the FPGA bitfile if the Clock100 PLL Unlocked
status is TRUE. Xilinx does not guarantee proper PLL operation
in these cases, and undesired behavior may occur. |
PXIe-797x Status
Items
Board IO FPGA I/O Items
| FPGA I/O Item | Description |
|---|---|
| Clock100 PLL Unlocked | Indicates if the PLL that generates the 40 MHz, 100 MHz, and 200
MHz base clocks has unlocked after the FPGA bitfile download. After
the FPGA bitfile downloads, the PLL locks to PXIe_CLK100 by default.
If PXIe_CLK100 is not present, the PLL locks to an onboard 100 MHz
oscillator. If the PLL unlocks from PXIe_CLK100 (due to a glitch on
the clock, for example) the FPGA then attempts to relock the PLL to
the 100 MHz oscillator. Note NI recommends
that you reload the FPGA bitfile if the Clock100 PLL Unlocked
status is TRUE. Xilinx does not guarantee proper PLL operation
in these cases, and undesired behavior may occur. |
| Device 3.3V Power |
Returns the power that the 3.3V power rail is consuming. The power consumption is indicated by the following formula: Power = P x 10 mW, where P is the value returned by LabVIEW. Therefore, a value of 150 indicates a power consumption of 1.5W (150 x 10 mW = 1.5 W). The default shutdown limit for this power rail is 9.7 W; do not exceed this limit. Do not exceed 37.75 W of power consumption between the 3.3V power rail and the 12V power rail. Exceeding this limit causes the FPGA to shut down. |
| Device 12V Power | Returns the power that the 12V power rail is consuming. The power consumption is indicated by the following formula: Power = P x 10 mW, where P is the value returned by LabVIEW. Therefore, a value of 150 indicates a power consumption of 1.5W (150 x 10 mW = 1.5 W). The default shutdown limit for this power rail is 35.5 W; do not exceed this limit. Do not exceed 37.75 W of power consumption between the 3.3V power rail and the 12V power rail. Exceeding this limit causes the FPGA to shut down. |
| Device Temperature | Returns the current temperature of the device, in increments of 1
°C. The temperature is measured from an onboard temperature sensor
on the PXIe-7972R PCB, external to the FPGA. Note The Device
Temperature terminal is synchronous to the 40 MHz clock, and it
should be accessed through that clock domain. Note The Device
Temperature interface requires some time to fully initialize
after FPGA download and reset operations. When performing an
FPGA download or reset, wait at least 250 ms before reading the
Device Temperature terminal. |
IO
Module Status FPGA I/O Items
| FPGA I/O Item | Description |
|---|---|
| EEPROM Power Enabled |
TRUE = Indicates that the adapter module EEPROM power rail is enabled. FALSE = Indicates that the adapter module EEPROM power rail is not enabled. |
| Expected IO Module ID | Reports the unique 32-bit IO Module ID that the currently downloaded FPGA VI is configured to use. The inserted IO Module ID must match the expected IO Module ID so the adapter module can function properly. The Expected IO Module ID is configured by choosing the appropriate adapter module in the IO Module General Properties dialog box and then recompiling and redownloading the FPGA VI. |
| Inserted IO Module ID | Reports the unique 32-bit IO module ID of the currently inserted adapter module. The Inserted IO Module ID must match the expected IO Module ID for the adapter module to function properly. |
| IO Module IO Enabled |
TRUE = Indicates that the adapter module connector FPGA I/O pins are enabled. FALSE = Indicates that the adapter module connector FPGA I/O pins are not enabled. Note These pins are
enabled only when an adapter module is connected, properly
powered, and when the FPGA has determined that the connected
adapter module is compatible with the FPGA VI currently
downloaded to the FPGA.
|
| IO Module Power Enabled |
TRUE = Indicates that the adapter module power is fully enabled. FALSE = Indicates that the adapter module power is not enabled. Note Adapter module
power is enabled only when an adapter module is connected and
the FPGA has determined that the connected adapter module is
compatible with the program currently downloaded to the
FPGA.
|
| IO Module Power Good | Reports the state of the power good signal on the adapter module connector interface. TRUE = Indicates that the connected adapter module power rails have had the proper amount of time to initialize and are operational and stable. FALSE = Indicates that the connected adapter module power rails are not ready. |
| IO Module Present | TRUE = Indicates that an adapter module is physically connected to the FPGA module. FALSE = Indicates that an adapter module is not connected to the FPGA module. |