Correct DRAM Access Size and Frequency

The access size is the amount of information stored in one memory address. You can set up memory to use a variety of data types. To achieve the best performance and to utilize the maximum amount of data, use a data type that matches the access size of the device. The access size is the exact number of bits that are written and read in a given memory access.

The following table shows the specifications for FlexRIO targets that support FPGA-accessible DRAM, including the optimum access size.

Note The PXI-7951, PXIe-7961, PXIe-7971, and PXIe-791x do not have DRAM.
FlexRIO Target Number of DRAM Banks Size per Bank Bandwidth per Bank Access Size Optimal Clock Rate
PXI-795x 2 64 MB 800 MB/s 64 bits 100 MHz
PXI-796x 2 256 MB 1.6 GB/s 128 bits 100 MHz
PXI-797x 1 2 GB 10.5 GB/s 512 bits 166 MHz
NI-793x 1 2 GB 10.5 GB/s 512 bits 166 MHz
PXIe-791x 2 2 GB 10.5 GB/s 512 bits 166 MHz

If you use a data type that is smaller than the access size, the remaining bits receive an unknown and invalid value, but still get written and take up both space and bandwidth. For example, if the access size is 128 bits wide and a 32-bit data type is chosen during configuration of the DRAM, there will be 96 bits of unknown and invalid data.

The following figure shows an optimized memory element and a memory element where the data type is smaller than the access size.



NI recommends using a data type that is the same width as the access size of the DRAM to optimize each access. Memory items accept a cluster as a data type and information can be packaged into clusters to achieve data types larger than those native to LabVIEW.

You can maximize bandwidth by pushing data into the memory item interface at the clock rate. NI recommends that you push data into the memory item interface within the Optimal Clock Rate specified in the table above.

Note Clock sources other than DRAM Clock can be used, although performance will not be optimized.