Random Access - 64 Bit Memory Interface

This memory interface provides the highest performance interface to external DRAM. Both the write-side and read-side data ports are exposed as 64-bit data words. Requests to write to and read from DRAM are satisfied by issuing a write or read command to the Random Access - 64 Bit memory interface.

The following table lists the I/O provided by the Random Access - 64 Bit memory interface.

Memory Interface I/O Data Type To Memory/From Memory Description
Address U32 To memory

Sets the address in external memory for reading or writing. The physical data bus for external memory is 16 bits wide (2 bytes). Each unique address value represents 2 bytes of data. Therefore, the total number of unique addresses in external memory is equal to (Memory Size in bytes)/2.

Note The memory interface exposed to LabVIEW FPGA is 64 bits wide. As a result, each memory write or read operation accesses four different address locations in memory. The memory controller latches this signal value only when you issue a new memory write command by asserting the Command_Write_Enable signal.
Command U8 To memory

0 = Performs a memory write.

1 = Perform a memory read.

The memory controller latches this signal value only when you issue a new memory write command by asserting the Command_Write_Enable signal.
Command_Write_Enable Bool From memory

TRUE = Performs either a memory write or read command, as dictated by the Command signal setting.

FALSE = Does not perform any new memory write or read commands.

To write or read a single 64-bit data value, assert this signal for only one clock cycle. Each new command is latched in a single clock cycle.
Command_FIFO_Full Bool From memory

TRUE = The memory controller internal command FIFO is full.

FALSE = Space is available in the command FIFO, and the memory controller can accept new commands.

Note Never assert the Command_Write_Enable signal when the Command_FIFO_Full signal is TRUE.
Read_Data_Upper U32 From memory Displays the upper 32 bits of the 64-bit data value that was read from external memory. When you issue a memory read command, this signal contains the data retrieved from external memory. The signal state is valid only on the clock cycles in which Read_Strobe is TRUE.
Read_Data_Lower U32 From memory Displays the lower 32 bits of the 64-bit data value that was read from external memory. When you issue a memory read command, this signal contains the data retrieved from external memory. The signal state is valid only on the clock cycles in which Read_Strobe is TRUE.
Read_Strobe Bool From memory

TRUE = Indicates that you can latch data onto the Read_Data_Upper and Read_Data_Lower signals.

FALSE = Indicates that you cannot latch data onto the Read_Data_Upper and Read_Data_Lower signals yet.

When you issue a memory read command, the memory read operation takes more than one clock cycle to complete. When the memory read completes, the Read_Strobe signal asserts TRUE for one clock cycle.

Note You must latch the Read_Data_Upper and Read_Data_Lower signals on the same clock cycle that Read_Strobe asserts.
Write_Data_Upper U32 To memory Sets the upper 32 bits of the 64-bit data value to be written to external memory. The memory controller latches this signal value only when you issue a new memory write command by asserting the Command_Write_Enable signal.
Write_Data_Lower U32 To memory Sets the lower 32 bits of the 64-bit data value to be written to external memory. The memory controller latches this signal value only when you issue a new memory write command by asserting the Command_Write_Enable signal.
Data Mask
Initialization_Done Bool From memory

TRUE = Indicates that the memory interface initialization sequence is completed.

FALSE = Indicates that the memory interface initialization sequence is not completed.

The memory controller performs its initialization sequence each time the FPGA is reprogrammed, and when the Reset Invoke Method function is called in the host VI.

Note Never assert Command_Write_Enable when the Initialization_Done signal is FALSE.

Each command that is written to the Random Access - 64 Bit memory interface is added to an internal command FIFO. This command FIFO can fill up, which drives the Command_FIFO_Full signal to TRUE. Do not issue any new commands to the Random Access - 64 Bit memory interface when the command FIFO is full.

The Random Access - 64 Bit memory interface automatically performs an initialization sequence after the FPGA is first programmed, and when the Reset Invoke Method function is called in the host VI. Do not issue new commands to the Random Access - 64 Bit memory interface before the initialization sequence is completed. The Initialization_Done signal returns to TRUE when the Random Access - 64 Bit memory interface initialization sequence is completed.

Each individual address value accesses 16 bits of data. Each write and read command writes and reads 64 bits of data, respectively. Because of this scheme, writing and reading data at consecutive addresses requires that you increment the address by 4 for each write and read command. Also, because each address value accesses 16 bits of data, the maximum number of valid addresses is equal to (Memory Size in Bytes)/2.

The Random Access - 64 Bit memory interface requires that you define the clock domain of the single-cycle Timed Loop from which it is being accessed. You can configure the clock domain in the Clock Selections property page for the corresponding DRAM bank item in the LabVIEW project. Configure the User_Clk signal to be driven with the LabVIEW FPGA clock resource that you are using to clock the single-cycle Timed Loop that is accessing the Random Access - 64 Bit memory interface I/O. All DRAM interface I/O added to the LabVIEW FPGA project by the Random Access - 64 Bit memory interface are synchronous to this User_Clk.

Note All memory interface signals must be used in a single-cycle Timed Loop.
Note You must disable all synchronization registers for all DRAM FPGA I/O signals (by setting the value to 0). The DRAM interface signals are synchronous to the DRAM interface clock. Synchronization registers causes a delay in sending and receiving data/commands to/from the DRAM interface. This delay can prevent proper operation. Always disable synchronization registers for synchronous interfaces where proper operation depends on no latency. All NI PXI version 1.1 and later CLIP items and all NI PXI Express CLIP items automatically disable all synchronization registers. For more information about disabling synchronization registers, refer to the Advanced Code Generation FPGA I/O Properties Page.