Pause Trigger Considerations for SC Express Devices

Note NI 433x devices and the NI 4340 do not support pause triggering.

The source of your sample clock often can affect when your acquisition pauses and resumes with the assertion and deassertion of a Pause Trigger.

Analog Input and Analog Output for Simultaneous Sampling SC Express Devices

When you generate analog output signals or acquire analog input signals on a simultaneous sampling SC Express device, such as the NI 4322 or NI 4300, the generation/acquisition pauses as soon as the Pause Trigger is asserted. If the source of your sample clock is the onboard clock, the generation/acquisition resumes as soon as the Pause Trigger is deasserted.



If you are using any signal other than the onboard clock as the source of your sample clock, the generation/acquisition resumes as soon as the Pause Trigger is deasserted and another edge of the sample clock is received, as shown in the following figure.



Analog Input for the NI 4353

The NI 4353 has three ADCs. There is ADC0, which is for the even analog input channels (for instance, ai4, ai6, and ai10), ADC1, which is for the odd analog input channels (for instance, ai1, ai3, and ai5), and ADC2, which is for the cold-junction compensation channels.

If the Pause Trigger is asserted, and you sample from multiple cold-junction compensation channels, multiple odd-numbered analog input channels, or multiple even-numbered analog output channels, the current sample across all channels finishes before pausing. For instance, if you are sampling eight channels, ai0:7, and ai4 is being sampled when the Pause Trigger is asserted, the remaining four channels complete their sample before the acquisition pauses. If you are using the onboard clock as the source of your sample clock, the acquisition resumes as soon as the Pause Trigger is deasserted.



If you are using any signal other than the onboard clock as the source of your sample clock, the acquisition resumes as soon as the Pause Trigger is deasserted and another edge of the sample clock is received, as shown in the following figure.



Analog Input for the NI 4357

The NI 4357 has five ADCs. The ADCs are staggered in the following ways:
  • ADC0 maps to the analog input channels ai0, ai5, ai10, ai15
  • ADC1 maps to the analog input channels ai1, ai6, ai11, ai16
  • ADC2 maps to the analog input channels ai2, ai7, ai12, ai17
  • ADC3 maps to the analog input channels ai3, ai8, ai13, ai18
  • ADC4 maps to the analog input channels ai4, ai9, ai14, ai19

If the Pause Trigger is asserted, and you sample from multiple channels on the same ADC, the current sample across all channels finishes before pausing. For instance, if you are sampling eight channels, ai0:7, and ai4 is being sampled when the Pause Trigger is asserted, the remaining four channels complete their sample before the acquisition pauses. If you are using the onboard clock as the source of your sample clock, the acquisition resumes as soon as the Pause Trigger is deasserted.



If you are using any signal other than the onboard clock as the source of your sample clock, the acquisition resumes as soon as the Pause Trigger is deasserted and another edge of the sample clock is received, as shown in the following figure.