Case Structure
- Updated2025-01-28
- 3 minute(s) read
Case Structure
Contains one or more subdiagrams, or cases, exactly one of which executes when the structure executes. The value wired to the case selector determines which case to execute.
![icon](https://docs-be.ni.com/bundle/labview-api-ref/page/structures/case-structure.png?_LANG=enus)
Components of a Case Structure
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![](https://docs-be.ni.com/bundle/labview-api-ref/page/structures/noloc_eps_callout_1.gif?_LANG=enus)
![](https://docs-be.ni.com/bundle/labview-api-ref/page/structures/noloc_eps_callout_2.gif?_LANG=enus)
![](https://docs-be.ni.com/bundle/labview-api-ref/page/structures/noloc_eps_callout_3.gif?_LANG=enus)
Configuring a Case Structure
Rearranging a Case Structure
Troubleshooting a Case Structure
FPGA Module Details
The following details apply when you use this object in an FPGA VI.
Single-Cycle Timed Loop | Supported. |
Usage | N/A |
Timing | Inside single-cycle Timed Loop--When you use a Case structure inside a single-cycle Timed Loop, the combinatorial logic delay required to evaluate the case selector is proportional to the width of the selector input data type and the number of cases. The combinatorial logic delay introduced by output tunnels is proportional to the number of cases. Outside single-cycle Timed Loop--When you use a Case structure outside a single-cycle Timed Loop, it takes one clock cycle to evaluate the case selector. Output tunnels require no clock cycles to execute and never include a register. |
Resources | The case selector requires FPGA resources proportional to the width of the input data type and the number of cases. Output tunnels require FPGA resources proportional to the width of the output data type and the number of cases. |
Notes | Complex Case structures can lead to long combinatorial paths and limit the maximum clock rate of a clock domain. |
Examples
Refer to the following example files included with LabVIEW.
- labview\examples\Structures\Case Structure\Case Structure - Selector Data Types.vi