Conditional Disable Structure

Has one or more subdiagrams, exactly one of which LabVIEW uses for the duration of execution, depending on the configuration of the conditions of the subdiagram. Use this structure when you want to disable specific sections of code on the block diagram based on some user-defined condition. Right-click the structure border to add or delete a subdiagram. When you add a subdiagram or right-click the structure border and select Edit Condition For This Subdiagram from the shortcut menu, you can configure conditions in the Configure Condition dialog box.


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You can configure conditions using predefined symbols or custom symbols.

After you create a Conditional Disable structure, you can add, duplicate, rearrange, or delete the subdiagrams. To scroll through the available subdiagrams, click the decrement and increment arrows in the selector label. You also can remove the structure without deleting objects in the structure. If multiple subdiagrams have conditions that are satisfied, only the first subdiagram will be enabled. If necessary, you can reorder the subdiagrams so that the desired subdiagram executes.

The Conditional Disable structure allows you to disable specific sections of code on the block diagram based on some user-defined condition. To disable specific sections of code on the block diagram based on compilation results, use the Type Specialization structure. To disable a section of a block diagram, use the Diagram Disable structure.

To switch to a Type Specialization or Diagram Disable structure, right-click the border of the Conditional Disable structure and select Replace with Type Specialization Structure or Replace with Diagram Disable Structure from the shortcut menu.

FPGA Module Details

The following details apply when you use this object in an FPGA VI.

Note The following details are subject to change with each version of the LabVIEW FPGA Module.
Single-Cycle Timed Loop Supported.
Usage When you use the Conditional Disable structure in an FPGA VI, LabVIEW evaluates the conditions at compile time and compiles only one subdiagram.
Timing Entering and exiting this structure requires no time on the FPGA.
Resources Only one subdiagram of the Diagram Disable structure compiles to the FPGA. Inactive subdiagrams consume no FPGA resources. The Diagram Disable structure itself also consumes no FPGA resources.

Examples

Refer to the following example files included with LabVIEW.

  • labview\examples\Structures\Disable Structures\Conditional Disable Structure.vi