While Loop
- Updated2025-01-28
- 3 minute(s) read
While Loop
Repeats the code within its subdiagram until a specific condition occurs. A While Loop always executes at least one time.
![icon](https://docs-be.ni.com/bundle/labview-api-ref/page/structures/while-loop.png?_LANG=enus)
Components of a While Loop
![](https://docs-be.ni.com/bundle/labview-api-ref/page/structures/loc_bd_While_loop.gif?_LANG=enus)
![](https://docs-be.ni.com/bundle/labview-api-ref/page/structures/noloc_eps_callout_1.gif?_LANG=enus)
![](https://docs-be.ni.com/bundle/labview-api-ref/page/structures/noloc_eps_callout_2.gif?_LANG=enus)
![](https://docs-be.ni.com/bundle/labview-api-ref/page/structures/noloc_eps_callout_3.gif?_LANG=enus)
FPGA Module Details
The following details apply when you use this object in an FPGA VI.
Single-Cycle Timed Loop | Not supported. |
Usage | The iteration (i) terminal is a 32-bit signed integer that saturates on reaching its maximum value, 2^31 - 1. |
Timing | The While Loop incurs two clock cycles of overhead between iterations. If the While Loop contains initialized shift registers, it takes one clock cycle before the first iteration to initialize shift register values. Code placed in a While Loop generally takes longer to execute than the same code placed in a single-cycle Timed Loop. |
Resources | The While Loop consists of a small state machine. Shift registers require FPGA resources in proportion to the width of the data type. Loop auto-indexers consist of a hidden shift register for each array element. |
Configuring a While Loop
- Creating a basic While Loop
- Adjusting the timing of execution
- Automatically processing each element in an array
- Accumulating data in arrays leaving loops
- Passing values between iterations
- Monitoring the Boolean value of a terminal for each loop iteration
- Converting a While Loop to a For Loop or Timed Loop
- Conditionally writing values to output tunnels