You can configure FlexRIO FPGA targets from the Project Explorer window. Complete the following steps to configure your FlexRIO FPGA target.

1. Create a new FlexRIO project or open an existing project.
2. Add an FPGA target to the project.
3. Right-click the FPGA target in the Project Explorer window and select Properties from the shortcut menu. The FPGA Target Properties Dialog Box appears.
4. Select General from the Category list.
5. Enter a Name for the FPGA target. The Name identifies the FPGA target in the Project Explorer window.
6. (Optional) If you did not select an existing target when you added the FPGA target to the project, enter a Resource for the FPGA target, which can be found in Measurement & Automation Explorer (MAX). The Resource associates the FPGA target in the Project Explorer window with a specific FPGA target connected to the development computer, network computer, or RT target.
7. (Optional) Specify the execution mode you want to use to debug an FPGA VI on the Execution Mode page.
   Note   LabVIEW displays only the options that the current FPGA target supports.
8. (Optional) Specify the top-level clock on the Top-Level Clock page.
9. (Optional) Add, create, or modify component-level IP declaration XML files on the Component-Level IP page.
10. (Optional) Configure target-scoped properties for accessing DRAM on the DRAM Properties page.
11. (Optional) Configure conditional disable symbols on the Conditional Disable Symbols page.
12. Click OK.