You can use the FPGA I/O Node to access the trigger lines on FlexRIO PXI devices. When developing an FPGA VI that uses triggers, be sure to reserve the trigger lines you are using and, to ensure compatibility with other FlexRIO devices, configure trigger pulses on FlexRIO PXI devices to last for at least two clock cycles of the clock on the receiving device. Refer to the PXI Specifications for more information about trigger bus requirements.