Inline Custom Devices with Asynchronous Loops

The RT Driver VI of an inline custom device can communicate channel data with VeriStand while launching an asynchronous loop(s) to handle nondeterministic operations.

One example of a nondeterministic operation is writing data to a log file. The RT Driver VI of the inline custom device communicates with the asynchronous loop(s) using RT FIFOs.

The following table displays the advantages and limitations of using this architecture when compared to inline and asynchronous custom devices.

Device Type Advantages Limitations
Inline custom devices

Allow you to read and write data to and from VeriStand in each iteration of the Primary Control Loop (PCL).

Allow you to access VeriStand system channels outside of your custom device.

Can introduce latency into the PCL as inline custom devices run inline with the PCL.
Asynchronous custom devices Allow you to execute large operations without introducing latency into the PCL. While you can synchronize the loop to the PCL, making the custom device pseudo-synchronous, pseudo-synchronous loops are not guaranteed to iterate once per iteration of the PCL nor are they guaranteed to iterate deterministically with respect to the PCL.
Inline custom devices with asynchronous loops

Allow you to read and write data to and from VeriStand in each iteration of the Primary Control Loop (PCL).

Asynchronous loop(s) handle nondeterministic operations, such as writing data to a log file, without introducing latency into the PCL.

Data must be consumed from the RT FIFOs at a fast enough rate or the mechanism will overflow.

Example: Embedded Data Logger

The Embedded Data Logger is an inline hardware interface custom device that reads and writes data to and from VeriStand in each iteration of the PCL. The Embedded Data Logger launches an asynchronous loop to log the data it receives to a file to avoid causing latency in the PCL that is associated with file I/O.

The following table displays actions the Embedded Data Logger takes to operate under this architecture.
Note You can find the Embedded Data Logger source code in the VeriStand Embedded Data Logger Custom Device repository on GitHub.
ActionDescription

Initializing RT FIFOs and launching an asynchronous loop

The Initialize case of the Embedded Data Logger RT Driver VI creates two RT FIFOs and launches an asynchronous loop. One RT FIFO communicates channel data from the Embedded Data Logger RT Driver VI to the asynchronous loop. The other RT FIFO communicates state information from the asynchronous loop to the Embedded Data Logger RT Driver VI.

The following diagram illustrates how the Embedded Data Logger and asynchronous loop execute with respect to the PCL and how the Embedded Data Logger communicates to the asynchronous loop via RT FIFOs.



Reading the status of the asynchronous loop in the inline custom device

One of the RT FIFOs created in the Initialize case passes status information from the asynchronous loop to the Embedded Data Logger RT Driver VI. You can see how the Embedded Data Logger RT Driver VI reads data from the RT FIFO by examining the Read Data from HW case. In this case, the Embedded Data Logger checks the RT FIFO for a change in the error value.

Sending channel data from the inline custom device to the asynchronous loop

The other RT FIFO sends channel data from the Embedded Data Logger RT Driver VI to the asynchronous loop. This communication takes place in the Write Data to HW case, specifically in the Sample Group Data VI that executes in this case. This VI is responsible for getting the values of the channels to log from the PCL and writing them to the RT FIFO so the asynchronous loop can access them.