Glossary

VeriStand uses unique terms for completing tasks while creating a project.

Use the following table to learn more about a term used in VeriStand.

Alphabetical order Term Description
A Alarm A notification that the value of a particular channel has gone outside a specified range of values. An alarm triggers the execution of a specified procedure.
Alias An alternate name for a channel in a system definition file.
B Bitfile A LabVIEW-generated file that defines the available I/O on the FPGA. A bitfile is a compiled version of an FPGA VI.
Block diagram A pictorial description or representation of a program or algorithm. In LabVIEW, the block diagram that consists of executable icons called nodes and wires that carry data between the nodes. The block diagram is the source code for the VI. The block diagram resides in the block diagram window of the VI.
C Calculated channel A channel that produces a new value based on calculations performed on other channels in the system.
Calibration The process of determining the accuracy of an instrument. In a formal sense, calibration establishes the relationship of an instrument's measurement to the value provided by a standard. When that relationship is known, the instrument may then be adjusted (calibrated) for best accuracy.
CAN (Controller Area Network) A serial bus finding increasing use as a device-level network for industrial automation. CAN was developed by Bosch to address the needs of in-vehicle automotive communications.
Chassis master hardware synchronization device A hardware device that controls the synchronization of all hardware in a PXI chassis or across multiple PXI chassis. The chassis master hardware synchronization device must be an NI-DAQ device with at least one analog input or output channel, any NI FPGA, or a timing and sync device that has the capability to drive the RTSI 0 line.
Custom device A virtual instrument that executes user-defined actions, such as third-party hardware control.
D Differential measurement system A way to configure a device to read signals, in which you do not need to connect either input to a fixed reference, such as the earth ground or a building ground.
DLL (Dynamic Link Library) A compiled model.
DMA (Direct Memory Access) A method by which data can be transferred to/from computer memory from/to a device or memory on the bus while the processor does something else. DMA is the fastest method of transferring data to/from computer memory.
Driver Software that controls a specific hardware device.
F FIBEX (FIeld Bus EXchange) A vendor-independent exchange format for embedded network data. It is an XML-based text format. For NI-XNET, NI adopted the ASAM FIBEX standard as a database storage format.
FIFO (First-In-First-Out memory buffer) The first data stored is the first data sent to the acceptor.
FIFO sink The output of a FIFO. You can use the VeriStand Custom Device APIs to set the buffer size at the source and sink of the FIFOs that an asynchronous custom device uses to share data with the real-time engine.
FIFO source The input of a FIFO. You can use the VeriStand Custom Device APIs to set the buffer size at the source and sink of the FIFOs that an asynchronous custom device uses to share data with the real-time engine.
FlexRay A new, deterministic, fault-tolerant, and high-speed bus system developed in conjunction with automobile manufacturers and leading suppliers.
FPGA (Field-Programmable Gate Array) A semi-conductor device that contains a large quantity of gates (logic devices), which are not interconnected, and whose function is determined by a wiring list, which is downloaded to the FPGA. The wiring list determines how the gates are interconnected, and this interconnection is performed dynamically by turning semiconductor switches on or off to enable the different connections.
FPGA configuration file An XML-based file that specifies the content of DMA FIFOs.
FPGA VI A configuration that is downloaded to the FPGA and that determines the functionality of the hardware.
Frames Messages sent across an embedded network. Frames are sorted into clusters within an NI-XNET database.
H HIL (Hardware-In-the-Loop) A simulation configuration in which you test a controller implementation with a simulated system.
Host computer The computer that runs the VeriStand Gateway and hosts the screen file.
I Interface The interface represents a single CAN, FlexRay, or LIN connector on an NI hardware device. Within NI-XNET, the interface is the software object used to communicate with external hardware described in the database.
L LabVIEW A graphical programming language.
LIN (Local Interconnect Network) A standard for low-cost, low-end multiplexed communication in automotive networks. LIN provides cost-efficient communication in applications where the bandwidth and versatility of CAN are not required.
M Mapping A connection between two channels.
MAX (Measurement & Automation Explorer) Provides a centralized location for configuration of NI hardware products. MAX also provides many useful tools for interaction with hardware.
MIO (Multifunction I/O) A DAQ module that designates a family of data acquisition products that have multiple analog input channels, digital I/O channels, timing, and optionally, analog output channels. An MIO product can be considered a miniature mixed signal tester, due to its broad range of signal types and flexibility. Also known as multifunction DAQ.
N NRSE (Non-Referenced Single-Ended mode) All measurements are made with respect to a common (NRSE) measurement system reference, but the voltage at this reference can vary with respect to the measurement system ground.
O Offline A simulation configuration in which you use software to simulate the controller and the system you want to control. No hardware is involved in an offline simulation.
P PCI (Peripheral Component Interconnect) An industry-standard, high-speed databus.
Phar Lap ETS A real-time operating system designed optimized for devices based on the Intel x86 architecture.
Port In regard to NI-XNET, port refers to the connector on an NI hardware device. The physical connector includes the transceiver cable if applicable.
Port width Refers to the number of lines in a port. For example, E Series devices have one port with eight lines; therefore, the port width is eight.
Procedure A set of actions that the VeriStand Engine executes.
Project file The .nivsprj file that defines high-level settings in an VeriStand project, such as the screen and system definition files to run, the IP address of the VeriStand Gateway, etc.
Q Quadrature encoder An encoding technique for a rotating device where two tracks of information are placed on the device, with the signals on the tracks offset by 90º from each other. This makes it possible to detect the direction of the motion.
R RAM (Random-Access Memory) The generic term for the read/write memory that is used in computers. RAM allows bits and bytes to be written to it as well as read from.
RCP (Rapid Control Prototype) A simulation configuration in which you test plant hardware with a software model of the controller.
RT (Real-Time) Pertaining to the performance of a computation during the actual time that the related physical process transpires so results of the computation can be used in guiding the physical process.
Real-time sequence A program that can deploy to a target with a system definition file and read/write channels defined in the system definition file. Real-time sequences can feature a wide array of programming constructs, including while loops, for loops, variables, and conditional statements. Real-time sequences execute on the target.
Reflective memory network A means of sharing data between two independent systems in a deterministic manner. Reflective memory devices are connected together using fiber optic cables. This reflective memory system forms a deterministic network that operates like a dual-ported memory system.
RSE (Referenced Single-Ended configuration) All measurements are made with respect to a common reference measurement system or ground. Also called a grounded measurement system.
RTSI bus (Real-Time System Integration) The NI timing bus that interconnects data acquisition devices directly by means of connectors on top of the devices for precise synchronization of functions.
S Screen file A .nivscreen or .nivsscr file that defines the configuration and settings for the screens and display items you view in the VeriStand Editor or Workspace.
SCXI (Signal Conditioning eXtensions for Instrumentation) The NI product line for conditioning low-level signals within an external chassis near sensors so that only high-level signals are sent to DAQ devices in the noisy PC environment.
Service A LabVIEW VI that runs on the host computer when VeriStand connects to a target. Services are typically Workspace tools that you want to launch as soon as you connect to a target, or that you want to synchronize with the launch of the Workspace window.
Single-point Data acquisition in which the software reads a single point of data from one or more analog input channels and immediately returns the value.
Stimulus profile A test executive that can call real-time sequences, open and close VeriStand projects, and perform data-logging and pass/fail analysis. It also connects real-time sequences to system definition files to bind channel data within the system definition file to variables in the real-time sequence. Stimulus profiles execute on the host computer.
Stimulus Profile Editor A development environment you use to create, modify, and execute tests.
System channel A channel that monitors the state and condition of various internal aspects of VeriStand.
System definition file A .nivssdf file you configure primarily in System Explorer. A system definition file contains the configuration settings of the VeriStand Engine.
T Target The desktop PC or real-time target on which you run the system definition file and VeriStand Engine.
TestStand NI test executive for sequencing and managing automatic test programs.
Timing and sync device A virtual instrument that synchronizes more than one chassis.
U User channel A channel that stores a single value.
V VeriStand Engine The non-visible execution mechanism that controls the timing of the entire system as well as the communication between the target and the host computer.
VeriStand Gateway The non-visible mechanism that creates a TCP/IP communication channel which facilitates communication with the VeriStand Engine over the network. The VeriStand Gateway receives channel values from the VeriStand Engine and stores these values in a table that can be viewed using the Channel Data Viewer.
VeriStand LabVIEW Model Generator A tool that generates a compiled model from a LabVIEW VI or simulation subsystem. This tool is accessible from the Tools menu in LabVIEW 2010 or later and generates files of the type .lvmodel or .lvmodelso.
Note You must install additional software to enable LabVIEW models for targets running a Linux Real-Time OS.
VI (Virtual Instrument) A LabVIEW program.
X XNET A suite of products that provide connectivity to Controller Area Network (CAN), Local Interconnect Network (LIN), and FlexRay networks.
XNET database A standardized file, such as CANdb (.dbc) or NI-CAN (.ncd) for CAN or FIBEX (.xml) for FlexRay that NI-XNET applications use to understand hardware communications in the embedded system. The database contains many object classes, each of which describes a distinct entity in the embedded system.