VeriStand New Features and Changes

Learn about updates — including new features and behavior changes — introduced in each version of VeriStand.

VeriStand 2025 Q1 New Features

VeriStand Steps for TestStand

VeriStand Steps for TestStand are sets of custom steps that allow you to automate VeriStand and develop/reuse test sequences for hardware-in-the-loop (HIL) systems.

This product is available for download using NI Package Manager, or at ni.com/downloads. Follow the prompts in NI Package Manager to install VeriStand Steps for TestStand.

Please refer to the VeriStand Steps for TestStand for more information on how to use this application.

LabVIEW 2025 Q1 Support

VeriStand is compatible with LabVIEW 2025 Q1 64-bit. All custom devices, LabVIEW models, and LabVIEW applications that contain the VeriStand API require this LabVIEW version. The VeriStand API will not install in previous versions of LabVIEW.

Enhanced VeriStand Model Generation Support for VeriStand IO Blocks

VeriStand Inport/Outport blocks now supports the enum data type, and can be connected to masked blocks and additional blocks like bus selector.

GCC Compiler Upgrade for VeriStand Model Generation Support

NI GCC Cross-Compiler for NI Linux Real-Time targets toolchain is upgraded to GNU C & C++ Compile Tools x64 2024Q4.

VeriStand 2024 Q3 New Features

FMI Support for Enum Data Type

Import FMUs with Inports/Outports/Parameters/Signals of type Enum as VeriStand channels.

Enhanced Debug Logging for Simulation Models in Target Log Viewer

Use the Target Log Viewer to understand debug information from FMUs, .vsmodels, and .lvmodels.

Simulink Model Enum Channels on VeriStand Screens

Scalar enum variables from .vsmodel and .fmu (3.0) are visible on VeriStand screens with their type definitions.

IP to FPGA Conversion Utility Supporting LV 2024 64-bit

IP to FPGA Conversion Utility 2024 Q3 now supports LabVIEW 2024 Q1 64-bit.

Support for Custom Reference Designs in HDL Coder Support Package for NI FPGA Hardware

The HDL Coder Support Package for NI FPGA hardware now includes support for custom reference designs, enabling the integration of Simulink models into existing LabVIEW FPGA projects.

VeriStand 2024 Q2 New Features

VeriStand Model Generation Support for Enum DataType

Use VeriStand Model Generation Support to import Inport/Outport/Signals/Parameter of type Enum from Simulink models as channels.

VeriStand Model Generation Support for VeriStand IO Blocks

Place VeriStand Inport/Outport blocks from VeriStand Model Generation Support anywhere in the subsystem hierarchy in your Simulink model to access them as model Inport/Outport channels.

APIs to Configure ECU Network Cluster

Configure Virtual ECU Clusters programmatically using APIs in the System Definition namespace.

Synopsys Silver FMI 3.0 Virtual ECU Support

Configure and execute Virtual ECUs from Synopsys Silver that follow the FMI 3.0 standard.

VeriStand 2024 Q1 New Features

LabVIEW 2024 Q1 Support

VeriStand is compatible with LabVIEW 2024 Q1 64-bit. All custom devices, LabVIEW models, and LabVIEW applications that contain the VeriStand API require this LabVIEW version. The VeriStand API will not install in previous versions of LabVIEW.

VeriStand Virtual ECU Toolkit

Use the VeriStand Virtual ECU Toolkit to integrate and execute virtual electronic control units (ECUs) for hardware-in-the loop (HIL) testing. Virtual ECUs allow you to test devices quickly, with a more realistic rest bus simulation, and with less effort for creating the bus simulation.

FMI 3.0 Support

VeriStand can configure and execute FMUs that follow the 3.0 standard. For more information on the support, refer to FMI Support.

VeriStand 2023 Q4 New Features

Alarm Monitor Displays Trip Message and Value

VeriStand Editor's Alarm Monitor now actively showcases Trip Messages across all three tabs (Active, History, Rules). Furthermore, it actively presents Values within the Active and History tabs. Additionally, the Alarm Log actively records both the Trip Message and Value for comprehensive tracking.

Revamped Launcher Interface

The VeriStand Launcher has undergone a significant transformation, introducing separate tabs for Projects and Learning. To access a collection of preloaded VeriStand projects and educational resources, navigate to the Learning tab. Meanwhile, the Projects tab offers access to Default Projects and enables users to incorporate their custom template projects seamlessly.

VeriStand Model Generation Support for Simulation States

With VeriStand Model Generation Support, you can now preserve the state of a .vsmodel file during execution, allowing for later restoration of the model using the saved state through an XML file. To save and restore states, use the .NET IModel method or the Screen/Workspace.

VeriStand 2023 Q3 New Features

VeriStand Model Generation Support for Importing Non-Virtual Bus Signals

Use VeriStand Model Generation Support to import non-virtual bus signals from Simulink models as channels. For more information, refer to How VeriStand Imports Models from the Model Generation Support MATLAB Add-on and the VeriStand Model Generation Support add-on documentation.

Python System Definition API

Use niveristand to script system definition (.nivssdf) files for use in the VeriStand Editor and deploy them to the VeriStand Engine. For more information, you can refer to the Getting Started With VeriStand documentation. Note that this feature supports multiple VeriStand versions.

Expanded VeriStand.exe Command Line Options

Use the command line to execute processes in VeriStand, including the ability to now open and close specific files or documents in a project. For more information on specific commands and their functionalities, refer to VeriStand Command Line Options documenatation.

Support for FMU Logging in VeriStand

Set the logging level for FMUs by editing a configuration file to debug failures. For more information on configuring the log levels, refer to FMI Support documentation.

VeriStand 2023 Q2 New Features

VeriStand Engine Performance

In System Explorer, the new default for the PCL DAQ timing source is Signal From Task (Sample Complete). This default applies to new projects when the timing source is set to DAQ Timing or Automatic Timing and there is a NI-DAQ device with at least one analog input hardware-timed single point channel.

The Signal From Task (Sample Complete) default option sends a tick to the PCL each time the Master DAQ device finishes acquiring an AI channel sample. This setting is beneficial for multiplexed DAQ modules with many channels. The setting has no impact on simultaneous sampled module behavior.

Other VeriStand Engine improvements include loop processing reductions for systems with a high count of channels, mappings, and faultable channels. Large systems, such as those with more than 20,000 channels and 10,000 mappings, can experience HP Loop duration reductions of more than 50 microseconds.

VeriStand Model Generation Support for Importing Signals

Use VeriStand Model Generation Support to import signals from Simulink models as channels. For more information, refer to How VeriStand Imports Models from the Model Generation Support MATLAB Add-on and the VeriStand Model Generation Support add-on documentation.

ESI File Importing

Import an EtherCAT Slave Information (ESI) file into VeriStand using the Scan Engine and EtherCAT Custom Device without installing LabVIEW. To begin importing the ESI file, open System Explorer and navigate to the custom device.

Screen Cluster Arrangement Options

Use additional cluster arrangement options on VeriStand screens to compact the appearance of large cluster hierarchies. To access these options in the VeriStand Editor, navigate to File » Preferences and click Screen to select a cluster arrangement.

IP to FPGA Conversion Utility supporting LV 2023 64-bit

IP to FPGA Conversion Utility 2023 Q2 now supports LabVIEW 2023 Q1 64-bit.

VeriStand 2023 Q1 New Features

LabVIEW 2023 Q1 Support

VeriStand is compatible with LabVIEW 2023 Q1 64-bit. All custom devices, LabVIEW models, and LabVIEW applications that contain the VeriStand API require this LabVIEW version. The VeriStand API will not install in previous versions of LabVIEW.

LabVIEW 2023 Q1 64-bit supports CompactRIO controllers and NI R Series modules. Custom devices and LabVIEW FPGA development can use LabVIEW 64-bit.

Note The HDL Coder Support Package for NI FPGA Hardware and IP to FPGA Conversion Utility only support LabVIEW 32-bit.

External Mode with XCP Communication

Enable external mode with XCP communication when building a MathWorks Simulink model to monitor signals and tune parameters from the Simulink environment. XCP provides additional capabilities such as viewing signals within referenced models. For more information, refer to the VeriStand Model Generation Support documentation on GitHub.

Terminal Specification for DAQmx Counter Operations

Use System Explorer or the System Definition .NET API to specify the following terminals for DAQmx counter tasks.

  • Terminal for counter I/O tasks.
  • A/B/Z terminal for position measurement tasks.

Specifying these terminals allows modules to use all counters through non-default PFI lines. For more information, refer to documentation for your module.

HDL Coder Support for PXIe R-series Kintex-7 and Simscape Models

HDL Coder Support Package for NI FPGA Hardware supports the following:

  • PXIe R-series Kintex-7 modules ─ Use the support package to remain within HDL Coder while generating a bitfile from a Simulink model for compatible NI FPGA hardware.
  • Simscape models.

VeriStand 2021 R3 New Features

Windows 11 Support

VeriStand now supports Microsoft Windows 11. For more information about NI support for Windows 11, refer to NI Product Compatibility for Microsoft Windows 11.

External Mode for Simulink Models

Enable external mode when building a model in MathWorks MATLAB Simulink® to monitor signals in Simulink. To access external mode and relevant documentation, download the VeriStand Model Generation Support add-on and refer to External Mode Simulations for Parameter Tuning, Signal Monitoring, and Code Execution Profiling.

For more information on VeriStand and Simulink models, refer to .

HDL Coder Support Package for NI FPGA Hardware

HDL Coder Support Package for NI FPGA Hardware enables access to NI FPGA hardware from HDL Coder. Use this package to remain within HDL Coder while generating a bitfile from a Simulink model. That bitfile can then be imported into VeriStand with the FPGA Addon custom device. To access this package, visit GitHub.

IP to FPGA Conversion Utility

IP to FPGA Conversion Utility supports the conversion of Simulink models into NI FPGA bitfiles. This utility uses a command line interface to convert models without opening LabVIEW. For more information on the utility, refer to the supplemental documentation.

AIM MIL-STD-1553 Custom Device

Use the AIM MIL-STD-1553 custom device to interact with AIM MIL-STD-1553 PXIe modules in VeriStand. To access this custom device, visit the AIM MIL-STD-1553 Custom Device repository on GitHub.

VeriStand 2021 R2 New Features

Deployment Command Center

Use the Deployment Command Center to execute HIL system validation tests by performing the following actions:

  • Deploy and undeploy a system configuration.
  • Connect and disconnect from local or remote gateways.
  • Update gateway communication settings.
  • Troubleshoot project and connection errors.

Access the Deployment Command Center from the VeriStand Editor by clicking the tab to the right of the home icon ().

Simulink Model Bus Support

Use virtual and non-virtual buses to organize Mathworks Simulink® software models.

Virtual buses are user interface aids that do not generate code. Non-virtual buses group elements in memory and can generate code.

Bus element support in .vsmodel inports, outports, and parameters is limited to the following data types:
  • Scalar
  • Vector
  • Numerical two-dimensional matrix
  • Boolean two-dimensional matrix
  • Scalar non-virtual bus

To access this support, generate models with version 1.1 of the VeriStand Model Generation Support add-on.

Custom Device LLB to PPL Conversion

Convert a LabVIEW library (LLB) custom device to packed project library (PPL) for the following benefits:
  • Improve deployment time by creating a smaller disk footprint.
  • Avoid load-time conflicts by granting each packaged custom device a copy of shared VI dependencies.
  • Avoid internal naming conflicts by preserving the file hierarchy.

Use inline and inline-async templates to convert your custom devices to PPL and use LabVIEW advanced packaging features. You can access these templates and relevant documentation from the VeriStand Custom Device Wizard repository on GitHub.

For more information, refer to the Custom Device Developer Handbook.

AIM ARINC 429 Custom Device

Use the AIM ARINC 429 custom device to interact with ARINC 429 PXIe modules in VeriStand using the AIM API. You can access this custom device from VeriStand Open Source Add-Ons on GitHub.

VeriStand 2021 New Features

VeriStand Editor

  • Add, delete, and configure alarms.
  • Use the Target Log Viewer to troubleshoot unexpected engine and custom device behavior.
  • View and adjust the target rate of a timing source from the VeriStand Editor configuration pane by clicking Document.

Supported Environments

VeriStand now supports the following LabVIEW environments.
  • LabVIEW 64-bit
  • LabVIEW RT 2021
Note All custom devices should be compiled in 64-bit.
VeriStand no longer supports the following real-time environments.
  • PharLap
  • Linux ARM Targets

Custom Devices

Build better custom devices with the following resources.

  • Use the Custom Device Handbook to extend the VeriStand environment with LabVIEW. The handbook provides background, design decisions, and technical information required to develop custom devices.
  • Use templates to convert your custom devices to PPL and use LabVIEW advanced packaging features. You can access these templates and relevant documentation from the Custom Device Wizard GitHub repository.

VeriStand Model Generation Support

Use VeriStand Model Generation Support MATLAB add-on to create VeriStand compatible models within the MathWorks Simulink® environment. Access this support natively from Simulink.

VeriStand 2020 R6 New Features

VeriStand Editor

Set the default appearance of channels on the screen. Click File » Preferences and select Screen to set the channel label location and cluster arrangement.

FPGA Addon Custom Device

FPGA Add-on Custom Devices now support all FXP datatypes that are also supported by LabVIEW. You can access this custom device from the VeriStand FPGA Add-on Custom Device repository on GitHub.

NI-SWITCH Custom Device

Use the G scripting API to modify a NI-SWITCH Custom Device. For more information, refer to Scripting Examples.lvproj in <Application Data>\LabVIEW 20xx\examples\NI VeriStand Custom Devices\Routing and Faulting. You can access this custom device from the VeriStand Routing and Faulting Custom Device repository on GitHub.

VeriStand 2020 R5 New Features

VeriStand Editor

  • Modify non-active mapping diagrams while a system definition is deployed. Editing in other tabs will not disturb the deployed system.
  • Create duplicates of a system definition file. Use copies of a system definition to easily deploy and test modifications without losing the original file.
  • Monitor array-type channels while the project is running.
  • Use C# to customize and extend the VeriStand Editor. You can access examples of implemented C# code from the VeriStand Editor Plug-in Examples repository on GitHub.

Control Keyboard Shortcut Behavior from the Command Line

Use the noDeployKeys command to prevent the use of the deploy and undeploy keyboard shortcuts during a session. You can still deploy and undeploy from the Operate menu.

FPGA Add-on Custom Device

  • Use the Scripting API to turn FPGA bitfiles into flexible and reusable system definition files.
  • Load and reload bitfiles without losing a previous configuration. Scalars and waveforms from a former bitfile remain imported while those that no longer exist are removed from the new bitfile.

You can access this custom device from the VeriStand FPGA Add-on Custom Device repository on GitHub.

Collect Memory Usage Data with the Telemetry Custom Device

Use the Telemetry Custom Device to understand the CPU and RAM usage of your system. You can access this custom device from the VeriStand Telemerty Custom Device repository on GitHub.

VeriStand 2020 R4 New Features

Launching VeriStand Silently

Deploy a system definition without launching the VeriStand Editor or System Explorer using the Windows Run command or from a language of your choice.

Instrument Add-on Custom Device

Use the Instrument Add-on custom device API to create a new instrument from a previously exported configuration. You can also use the API to add messages and to configure the command and response functionality. For more information, refer to the VeriStand Instrument Add-on Custom Device repository on GitHub.

ASAM XIL Steps for TestStand

Use the <UndeployVeriStandProjectOnDisconnect> tag in the port configuration XML file to specify if VeriStand is undeployed when the Framework is cleaned up.

Alarm Status Channel

Monitor the state of one or more alarms in the VeriStand engine with an alarm status channel. You can use these channels in custom devices and real-time sequences to determine what actions to take when an alarm state changes.

Stopping Groups of Real-Time Sequences with Procedures

Create a procedure to stop a specified group of real-time sequences and skip to their clean-up sections. You can use the procedure to shut down sequences related to a specific device under test (DUT) in a multi-DUT scenario. Use the Stimulus Profile Editor to assign a group to a real-time sequence call step.

VeriStand 2020 R3 New Features

VeriStand Editor

  • On the Mapping Diagram, use the Focus command (<Ctrl+,>) to emphasize all mappings and nodes connected to a selected item. Using Focus will highlight all directly connected components while fading the rest of the system.
    Note You can interact with faded items while using Focus.
  • In the System Definition pane, right-click an item and select Locate in System Explorer to navigate to the place in System Explorer where that item is configured.

XNET Status Channels

Monitor the XNET bus statuses for CAN, LIN, and FlexRay from VeriStand. In System Explorer, right-click an XNET port and select Add Port Specific Channels to add status channels to the system definition.

FMU Fixed Parameters

Set initial values for Functional Mockup Unit (FMU) initialization parameters during deployment through a text file. You can also set fixed parameter values before running a deployed model.

FPGA Add-on Custom Device

Use the FPGA Add-on custom device to run an FPGA bitfile without implementing the normal VeriStand FPGA template. The add-on allows the transfer of basic scalar data types inline with VeriStand's primary control loop (PCL) and supports reading and writing waveforms with FPGA DMA channels. You can access this custom device from the VeriStand FPGA Add-on Custom Device repository on GitHub.

Instrument Add-on Custom Device

Use the Instrument Add-on custom device to communicate with instrumentation, such as power supplies, environmental chambers, and emissions equipment, over various protocols. The device supports serial, GPIB (using NI VISA), ethernet (TCP, UDP, and NI VISA), AK serial, and AK TCP. You can access this custom device from the VeriStand Instrument Add-on Custom Device repository on GitHub.

VeriStand 2020 R2 New Features

VeriStand Editor

  • Manage aliases and user channels without using System Explorer.
  • Use the Model Signal Viewer to check signal values while a project is running.
  • Receive warnings when a disk model is out of sync with the loaded system definition model.

FlexRay

Enable the FlexRay Allow Passive to Active property to permit the transition from the normal-passive to the normal-active state.

CAN

Create channels to view timing information for individual CAN multiplexer modes independent of the overall frame.

VeriStand 2020 New Features

Mapping Diagram

The following tasks can be completed on the Mapping Diagram.

  • Manage Calculated Channels⁠ — You can now create, modify, and delete calculated channels from the Mapping Diagram.
  • View unmapped channels and mappings — Use the Mapping Diagram Table View to see unmapped channels and mappings in the system definition. You can filter the table by selecting a node or wire.

Embedded Data Logger Custom Device Available on GitHub

The Embedded Data Logger is now an open-source custom device that installs separately from VeriStand. You can access this custom device from the VeriStand Embedded Data Logger Custom Device repository on GitHub. The 20.0 version includes the ability to automatically split and archive log files.

Scripting Routing and Faulting Custom Device Elements

Use the LabVIEW API to script Routing and Faulting Custom Device elements and automate fault insertion in VeriStand. The API is supported in LabVIEW 2017 and newer. For more information, refer to the VeriStand Routing and Faulting Custom Device repository on GitHub.

Support for DAQmx Waveform Logging

VeriStand now supports DAQmx Waveform Tasks on CompactRIO with DAQmx Controllers. This enables per-slot support with DAQmx, FPGA, XNET, and Scan Engine on supported controllers.

CAN FD Scripting

The VeriStand .NET API now supports scripting CAN ports with CAN FD baud rates and custom bitfields.

VeriStand 2019 R3 New Features

Mapping Diagram

The following tasks can be completed on the Mapping Diagram.

  • Add and configure simulation models on the diagram from the palette.
  • Evaluate items, such as channels and mappings, that have been added or removed on the Mapping Diagram. These items are highlighted after completing actions such as swapping a model or altering the system definition.

MathWorks Simulink® Software Model Toolchain Support

VeriStand now supports models from Simulink software versions R2019a and R2019b for Windows and Linux only. VeriStand also supports compiling Simulink models for Windows using a MinGW-w64 compiler.

TDMS File Viewer Support for DIAdem

VeriStand now integrates DIAdem as its default TDMS file viewer.

Routing and Faulting Custom Device

Use the Routing and Faulting Custom Device's switching and fault insertion modules to inject faults. For more information, refer to the VeriStand Routing and Faulting Custom Device repository on GitHub.

The Routing and Faulting Custom Device also supports SLSC Switch hardware and additional hardware. The SLSC Switch Custom Device is a VeriStand add-on that supports SLSC routing modules. The following modules are supported:

  • SLSC-12251
  • SLSC-12252
  • SET-2010

SLSC Switch routing modules can be found in System Explorer under Targets » Controller » Hardware » SLSC » SLSC Chassis » Modules » Slot (n).

VeriStand 2019 R2 New Features

The following tasks can be completed on the Mapping Diagram.

  • Map channels and aliases — Use wires to connect and disconnect mappings.
  • Specify a target — Select a target and use the Document pane to designate the name, operating system, and IP address.
  • Remove a model or calculated channel — Click and delete a model or calculated channel to remove it from the system definition.
  • Customize terminal placement — Right-click a node and hover over Terminal Placement to choose the side of the node that inputs and outputs appear.
  • Change a channel's name — Right-click a channel and select Rename Channel.
  • Reorder channels — Click, hold, and drag the left corner of a channel to rearrange the list. You can also click a channel and use the Search dialog box to select another channel to switch them.

VeriStand 2019 New Features

VeriStand Editor

You can now use the VeriStand Editor to control aspects of your project. The UI Manager and Project Explorer windows from previous releases of VeriStand have been combined into one editor. Many of the features of the Project Explorer window can now be accessed through Project Files in the Navigation pane of the VeriStand Editor. The VeriStand Editor also contains the Mapping Diagram to help visualize channel mappings.

Note You can access the interface from previous versions of VeriStand by launching the VeriStand Project Explorer from the x86\NI\VeriStand 2019 directory.

Mapping Diagram

You can now visualize software mappable points within a VeriStand project with the Mapping Diagram. This graphical diagram allows you to see all VeriStand channels and the mappings between them.

Groups of mappings between two nodes are automatically bundled into a single wire by default to reduce clutter. If a wire represents multiple mappings, you can select the bundle to see more information in the Configuration pane.

Other features of the Mapping Diagram include the ability to:

  • Display aliases and user channels
  • Validate and debug mappings

PXI NI Linux RT Support

You can now deploy System Definition Files to PXI NI Linux RT targets similarly to previously supported targets. Benefits of supporting the NI Linux RTOS include:

  • Support for newer compilation tools and advance C++ features.
  • Support for Linux and other libraries.
  • Improvement of memory handling and computational power.

Custom Device Support

VeriStand 2019 officially supports the following custom devices.

  • Engine Simulation Toolkit — Provides a configuration-based experience for validating engine control units (ECUs).
  • Scan Engine and EtherCAT — Supports easily read scanned I/O from C series modules in a CompactRIO or NI 914x EtherCAT chassis. This custom device also supports custom FPGA personalities to be used with a 914x chassis.
  • SLSC 12201 DIO Module Custom — Integrates the SLSC-12201 33 V Digital I/O Conditioning Module into VeriStand.
  • SLSC EDS Custom Device — Allows any generic SLSC Capabilities file to be used in VeriStand.
  • Synchronization Custom Device — Synchronizes RT system time and PXI chassis clocks.

These custom devices can be downloaded with VeriStand 2019 using NI Package Manager. Check NI GitHub for updates and other custom devices.

CAN FD Support

VeriStand 2019 supports XNET implementation for the Controller Area Network Flexible Data-Rate (CAN FD) protocol. With a XNET implementation, you can now use databases that support CAN FD and CAN FD with Baud Rate Switching I/O modes. This implementation also allows calculating and using custom baud rates for a CAN interface. For more information on CAN FD, see Understanding CAN with Flexible Data-Rate (CAN FD).

FMI Support

VeriStand now has limited support for the Functional Mockup Interface (FMI) API standard on Windows and PXI LinuxRT. Use the FMI standard to create tool agnostic, portable solutions between modeling and simulation environments. VeriStand enables the configuration and execution of FMI 2.0 CoSimulation models on host and National Instruments Real-Time Linux64 systems.

Note This support requires the Functional Mockup Units (FMUs) to have the proper executable binaries available.