Counter n Sample Clock Signal

Use the Counter n Sample Clock (CtrnSampleClock) signal to perform sample clocked acquisitions and generations.

You can specify an internal or external source for Counter n Sample Clock. You also can specify whether the measurement sample begins on the rising edge or falling edge of Counter n Sample Clock.

If the sbRIO controller receives a Counter n Sample Clock when the FIFO is full, it reports an overflow error to the host software.

Using an Internal Source

To use Counter n Sample Clock with an internal source, specify the signal source and the polarity of the signal. The source can be any of the following signals:

  • DI Sample Clock

  • DO Sample Clock

  • AI Sample Clock

  • AI Convert Clock

  • AO Sample Clock

  • DI Change Detection output

Several other internal signals can be routed to Counter n Sample Clock through internal routes. Refer to "Device Routing in MAX" in the NI-DAQmx Help or the LabVIEW Help for more information.

Using an External Source

You can route any of the following signals as Counter n Sample Clock:

  • Any PFI terminal

  • Analog Comparison Event

You can sample data on the rising or falling edge of Counter n Sample Clock.

Routing Counter n Sample Clock to an Output Terminal

You can route Counter n Sample Clock out to any PFI terminal. The PFI circuitry inverts the polarity of Counter n Sample Clock before driving the PFI terminal.