PXIe-5644/5645/5646 Instrument Design Libraries

The following table describes the instrument design libraries that you can use to create application-specific instrumentation with the PXIe-5644/5645/5646 modules. Refer to the LabVIEW context help for details of each VI.

Note The PXIe-5840 does not support the Instrument Design Libraries.
Instrument Design Library Short Description LabVIEW Palette Type
Configuration* RF Input Use these VIs to configure reference level, frequency, and other aspects of the RF input subsystem. Host and FPGA
RF Output Use these VIs to configure power level, frequency, and other aspects of the RF output subsystem. Host and FPGA
IQ Input Use these VIs to configure the vertical range and other aspects of the I/Q input subsystem. Host and FPGA
IQ Output Use these VIs to configure the output level, analog offsets, and other aspects of the I/Q output subsystem. Host and FPGA
Basecard Use these VIs to configure clocks and other features of the basecard subsystem. Host and FPGA
PXIe-5644 Use these VIs for aggregated configuration of RF input, RF output, and basecard subsystems. FPGA
PXIe-5645 Use these VIs for aggregated configuration of RF input, RF output, I/Q input, I/Q output, and basecard subsystems. FPGA
PXIe-5646 Use these VIs for aggregated configuration of RF input, RF output, and basecard subsystems. FPGA
Multirecord Acquisition Use these VIs to perform record-based waveform acquisition using DRAM on the device. Host and FPGA
Waveform Sequencer Use these VIs to perform arbitrary waveform generation, waveform linking and looping, generation of markers, and advanced triggering. Host and FPGA
Digital Signal Processing (DSP) Use these VIs to digitally process I/Q data. These VIs include the functions typically found in digital downconverters (DDCs), digital upconverters (DUCs), and DSP for digital correction of analog imperfections in the system. FPGA
Register Bus Use these VIs to send register read and write instructions from your application on the host to the FPGA. Host and FPGA
Embedded Configuration (ECB) Use these VIs to store multiple hardware configurations in onboard memory and recall them from the FPGA. This allows the FPGA to reconfigure the hardware without intervention from the host. Host and FPGA
Trigger Synchronization Use these VIs to synchronize triggers on multiple devices. FPGA
FIFO Use these VIs to read and write FIFOs. These VIs implement the four-wire handshaking protocol and support four commonly used data types. FPGA
Memory Use these VIs to access SRAM and DRAM memories on the device in a consistent manner. FPGA
Basic Elements Use these VIs to detect rising and falling edges, and to store Boolean values. FPGA
*Encompasses the RF IN, RF OUT, I/Q IN, I/Q OUT, Basecard, PXIe-5644, PXIe-5645, and PXIe-5646 palettes.