FPGA Desktop Execution Node

Runs an FPGA VI on a development computer with simulated I/O for the specified number of clock ticks. This node writes all inputs, passes the amount of simulated time you specify, then reads all outputs. The FPGA VI pauses execution until the FPGA Desktop Execution Node is called again, at which point the FPGA VI resumes for the specified number of clock ticks.


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Dialog Box Options

Option Description
Simulation Configuration Contains the following options:
  • VI—Specifies the FPGA VI to run.
    • Browse VI—Displays the Select VI dialog box. Click this button to select the VI you want to reference.
  • Reference Clock—Specifies an available FPGA clock to use as the timing source for simulated time.
  • Clock Ticks—Specifies the number of clock ticks to run the FPGA VI for each call to the node. You must specify a non-zero integer.
Terminal Configuration Contains the following options:
  • Available Resources—Displays the I/O resources and front panel controls and indicators available for simulating with the FPGA Desktop Execution Node. The FPGA target you specify in the VI selection box determines the resources that appear in the Available Resources tree.

    Click the Add/Remove buttons to the right of the Available Resources list to add and remove resources.

  • Selected Resources—Displays the list of resources you select from the Available Resources tree.
  • Change Terminal Direction—Contains the following options:
    • In—Specifies that the selected resource has an input terminal on the block diagram.
    • Out—Specifies that the selected resource has an output terminal on the block diagram.
    • In/Out—Specifies that the selected resource has both input and output terminals on the block diagram.

Inputs/Outputs

Parameter Description
Error In

error in describes error conditions that occur before this node runs. This input provides standard error in functionality.
Error Out

error out contains error information. This output provides standard error out functionality.

You must set the execution mode of the target to Simulation (Simulated I/O). You cannot use this node with a custom VI for FPGA I/O. You cannot use this node with Component-Level IP I/O. You cannot use this node with the User-Controlled I/O Sampling functions.

If you want to simulate your code continuously, you must place your LabVIEW FPGA code inside a While Loop.

Related Information

Debugging with the FPGA Desktop Execution Node

Testing and Debugging LabVIEW FPGA Code

Using the LabVIEW FPGA Desktop Execution Node

Examples

Refer to the following example files included with LabVIEW FPGA Module.

  • labview\examples\CompactRIO\FPGA Fundamentals\Simulation\Simulating Analog Signals with the DEN\Simulating Analog Signals with the DEN.lvproj
  • labview\examples\CompactRIO\FPGA Fundamentals\Simulation\Simulating Digital Signals with the DEN\Simulating Digital Signals with the DEN.lvproj
  • labview\examples\R Series\FPGA Fundamentals\Simulation\Simulating Analog Signals with the DEN\Simulating Analog Signals with the DEN.lvproj
  • labview\examples\R Series\FPGA Fundamentals\Simulation\Simulating Digital Signals with the DEN\Simulating Digital Signals with the DEN.lvproj