Generate SRM Linear Model FPGA Data VI
- Updated2023-02-21
- 5 minute(s) read
Generate SRM Linear Model FPGA Data VI
Owning Palette: Switched Reluctance Motor VIs
Requires: Electric Motor Simulation Toolkit
Generates data and parameters for simulating a switched reluctance motor (SRM) on FPGA targets using the linear model function.
This VI prepares the FPGA data on the desktop, and thus reduces the workload of calculations on FPGA targets.
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SRM linear model parameters specifies the parameters describing the linear model of an SRM.
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SRM type specifies the number of poles and phases in the electric motor.
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mechanical parameters specifies the mechanical parameters of the electric motor. The mechanical parameters impact the forces and movement of the motor.
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initial rotor position specifies the mechanical rotor position, in degrees, when the motor starts. The default value is 0. | ||||||||||||
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error in describes error conditions that occur before this node runs. This input provides standard error in functionality. | ||||||||||||
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dt specifies the time interval, in seconds, at which LabVIEW simulates the electric motor. The value of dt must be greater than 0. | ||||||||||||
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resistance specifies the resistance, in ohms, of the electric motor. The value of resistance must be greater than 0. | ||||||||||||
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SRM linear model parameters on FPGA returns a reference to the SRM linear model, which you can use to simulate an electric motor on an FPGA target. Use the front panel controls in an FPGA VI to transfer the motor parameters from the host computer to an FPGA target. | ||||||||||||
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model initial state returns information about the SRM linear model at the starting time. Use the information of initial state for calculations on FPGA targets later.
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error out contains error information. This output provides standard error out functionality. |
Example
Refer to the SRM Linear Model Configuration VI in the labview\examples\Electric Motor Simulation\SRM\SRM Linear Model Configuration directory for an example of using the Generate SRM Linear Model FPGA Data VI.