Multiply Function

Returns the product of the inputs.

If you wire two waveform values or two dynamic data type values to this function, error in and error out terminals appear on the function. The connector pane displays the default data types for this polymorphic function.


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Inputs/Outputs

  • cdbl.png x —

    x can be a scalar number, array or cluster of numbers, array of clusters of numbers, and so on.

  • cdbl.png y —

    y can be a scalar number, array or cluster of numbers, array of clusters of numbers, and so on.

  • idbl.png x*y —

    x*y is the product of x multiplied by y.

    • You cannot use this function to multiply a matrix and a vector. Use the A x B VI instead.

    When multiplying two matrices, if the number of rows in the second matrix does not match the number of columns in the first matrix, this function returns an empty matrix. Refer to the A x B VI for more information about matrix multiplication.

    When you wire matrix data as an input to this function, a VI that includes subVIs that work with the matrix data type replaces the function. The resulting VI has the same icon but contains a matrix-specific algorithm. The node remains a VI if you disconnect the matrix from the input(s). Wire other data types as inputs to restore the original function. If you wire a data type to a function and that data type causes a basic math operation to fail, the function returns an empty matrix or NaN.

    Fixed-Point Details

    If you wire fixed-point values to Numeric functions such as Add, Subtract, Multiply, and Square, the functions usually return values that do not lose any bits of word length. However, if the operation creates a value that exceeds the maximum word length that LabVIEW accepts, overflow or rounding conditions can occur. LabVIEW accepts a maximum word length of 64 bits. Use the Numeric Node Properties dialog box to configure how LabVIEW handles overflow or rounding of fixed-point data.

    FPGA Module Details

    The following details apply when you use this object in an FPGA VI.

    Note The following details are subject to change with each version of the LabVIEW FPGA Module.
    Single-Cycle Timed Loop Supported.
    Usage

    Most FPGA targets contain a limited number of embedded multipliers. The FPGA Module compiler uses embedded multipliers to implement multiply operations until it occupies all the embedded multipliers. If the FPGA target runs out of embedded multipliers, the compiler uses generic logic gates instead, and the Multiply function becomes expensive in terms of FPGA resource usage.

    If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications.
    Timing

    Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x or y, whichever data type is larger.

    Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register.

    If you use this function with the fixed-point data type, the overflow and rounding modes might impact timing.

    Resources This function requires FPGA resources proportional to the number of bits in x or y, whichever data type is larger. Consider using the smallest data type possible to optimize FPGA VIs. If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources.
    Notes You also can use the High Throughput Multiply function to perform fixed-point math and analysis on an FPGA target.

    Examples

    Refer to the following example files included with LabVIEW.

    • labview\examples\Numerics\Numeric Functions.vi