The LabVIEW FPGA Module includes a feature for HDL IP integration called component-level IP (CLIP).

FlexRIO devices support two types of CLIP: user-defined CLIP and socketed CLIP.

• User-defined CLIP—Allows you to insert HDL IP into an FPGA target, enabling VHDL code to communicate directly with an FPGA VI.
• Socketed CLIP—Provides the same IP integration functionality of the user-defined CLIP, while also allowing the CLIP to communicate directly with circuitry external to the FPGA. Adapter module socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external adapter module connector interface or the FlexRIO FPGA module onboard DRAM.

The following illustration shows the relationship between an FPGA VI and CLIP.

To configure your adapter module using the LabVIEW FPGA module, you can do one of the following things:

• Configure a FlexRIO Adapter Module in LabVIEW.
• Configure a Custom Adapter Module in LabVIEW.

For information about using LabVIEW FPGA to access the onboard DRAM, refer to the DRAM Interfaces.