Archived: LabVIEW Communications 1.1 to 2.0 Migration Guide for FlexRIO Projects

This document covers LabVIEW Communications 1.1 to 2.0 Migration Guide for FlexRIO Projects.

The guide is made up five documents covering the following topics: 

• 802.11 Application Framework
• LTE Application Framework
• USRP Projects
• FlexRIO Projects
• General Projects

Each section discusses the required steps to migrate that specific type of project. For example, if you would like to migrate a USRP streaming project, you should navigate to the USRP Projects section for guidance. If your project does not fall into the first three categories listed above, you should navigate to the General Projects section. Each section is meant to be self-contained and used independently of the others, so redundant information may be included in multiple sections.

Note: Always back up a copy of the original project before attempting any migration efforts.

This section describes the steps necessary for reusing a project that was initially based on the FlexRIO API and example projects in LabVIEW Communications 2.0.

This section includes the following subsections. Use the one that is most appropriate for the type of FlexRIO project you are migrating.

• PXIe NI-579xR Streaming

PXIE NI-579XR Streaming

FPGA and System Resources

Projects using 579x targets will have broken FPGA VIs that reference the “Sample Clock”. This clock has been renamed to the “Data Clock” and must be reconfigured. Additionally, the register bus FIFO has changed. Hence, an FPGA bitfile rebuild is required.

The following steps demonstrate the changes for the basic NI 5971 Rx and Tx portions of the PXIe NI-579x Streaming project. However, these same changes can be duplicated for the other NI 579x and MIMO portions.

1. Create a backup of your project.
   
2. Open your project in LabVIEW Communications 2.0.
   
3. Click Yes to convert as shown in Figure 92.

Figure 92: Convert Dialog

4. Ensure that newly created resource document matches the correct target name. For example, “5791 Resources.grsc”.
   
5. Delete the following items from “5791Resources.grsc”:
   
   a. reg.host instruction fifo 0

Figure 93: Files to Delete from “5791 Resources.grsc”

6. Open the “Streaming Xcvr (NI 5791) (FPGA).gvi”.
   
7. Change references from “Sample Clock” and “Sample Clock x2” to “Data Clock” and “Data Clock x2” respectively.  

Figure 94: Data Clock References in “Streaming Xcvr (NI 5791) (FPGA).gvi”

8. Change the reference input on “Process.gcdl” to the new register bus FIFO “niInstr Register Bus v0.grsc\reg.host instruction fifo 0” as shown in Figure 95.

Figure 95: Updated Register Bus in “Streaming Xcvr (NI5791) (FPGA).gvi”

9. Allow all document changes to finish loading and save all files.
   
10. Compile the FPGA VI.
    
    a. Open the System Designer (in the “Project Files” view of the Navigation Pane on the left) by double-clicking on the top project file.
    b. Select the FPGA top-level under the target you want to build the bitfile for.
    c. Click Build on the right pane as shown in Figure 96.

Figure 96: Compile the Project

11. (Recommended) Once the bitfile is finished building, exclude it from the project as shown in Figure 97 and include it again. This will ensure that the latest changes are actually applied.

Figure 97: Option to Exclude Bitfile

 
Host-Side

The FIFO resource names in the Host subVIs that interface with DMA FIFOs must be updated. This includes VIs which aren't in VI.lib (Sample Project VIs and User VIs). In LabVIEW Communications 2.0, the FIFO resource contains additional prefixes for the FPGA resource file name along with the FIFO name itself. For example, “Host Tx Stream” becomes “5791 Resources.grsc\Host Tx Stream.” All FIFO node instances (Start/Stop, Configure, and Read/Write), along with any FPGA reference terminals, must be updated.

Use your newly compiled bitfile from step 10 above to get access to the DMA FIFO references required.

1. Open the “Configure Stream.gvi” in the <project directory>\Host SubVIs folder of your project.
   
   a. Navigate to the “tx” case.
   b. Select the "ConstantData1" terminal and in the right-hand rail click Configure.

Figure 98: Right-Hand Rail Configure Option for “ConstantData1” 

i. In the “FPGA Interface Dynamic Refnum Configuration“ dialog, click Import bitfile and browse to your recently compiled bitfile.

Note: The default location will be in the <project directory>\Builds folder but this, along with the file name, will vary based on the configuration of the build spec used during compile.

Figure 99: Import Bitfile

ii. (Optional) With the “FPGA Interface Dynamic Refnum Configuration“ dialog still open, remove all unused resources by clicking the X symbol on the right side.

Note: This will not affect functionality but may make it easier to view used resources at a later time.

iii. Click OK in the “FPGA Interface Dynamic Refnum“ dialog.

c. Repeat this for “ConstantData1_2”.

Figure 100: Right-Hand Rail Configure Option for “ConstantData1_2”

d. Navigate to the “rx” case to repeat this process for “ConstantData2” and “ConstantData2_2”

Figure 101: Update References in “rx” Case
 
e. Update to the new DMA FIFO's in each Case Structure for each “rx” and “tx” case as well as any nested Case Structures. Each case will contain one, or more, FIFO nodes of a Start DMA FIFO, Stop DMA FIFO, and Configure DMA FIFO. Using the right-hand rail configuration, update each FIFO node to the following:

i. Host Tx Stream » 5791 Resources.grsc\Host Tx Stream
ii. Host Rx Stream » 5791 Resources.grsc\Host Rx Stream

Figure 102: Update DMA FIFOs

2. Follow the same general steps from step 1 for the "Fetch Rx Data (CDB WDT).gvi" in the <project directory>\Host SubVIs folder of your project.
   
   a. Update the following Read DMA FIFOs as shown in Figure 103.

i. Host Rx Stream » 5791 Resources.grsc\Host Rx Stream
ii. Host Rx Stream » 5791 Resources.grsc\Host Rx Stream

Figure 103: Update FIFOs and References for “Fetch Rx Data (CDB WDT).gvi”

3. Follow the same general steps from step 1 and step 2 for the “Write Tx Data (I16 multi).gvi” in the <project directory>\Host SubVIs folder of your project.
   
   a. Update the following Read DMA FIFOs as shown in Figure 104.

i. Host Tx Stream » 5791 Resources.grsc\Host Tx Stream
ii. Host Tx Stream » 5791 Resources.grsc\Host Tx Stream

Figure 104: Update FIFOs and References for “Write Tx Data (I16 multi).gvi”

4. Configure the Open FPGA VI Reference to select the newly compiled bitfile generated from the previous section. Do this for “Tx Streaming (Host).gvi”, “Rx Streaming (Host).gvi”, or any top-level VI in the project that will be referencing the FPGA.

Figure 105: Update the Bitfile Reference on “Tx Streaming (Host).gvi”

5. (Optional) Configure the Amplitude input on the “Generate Waveform.gvi”. The default setting is 1, but this may cause DSP overflow warnings.

Figure 106: Lowering the Amplitude Setting for the “Generate Waveform.gvi”

Note: Similar changes must be made if any DMA FIFO's were added to the project in previous versions of LabVIEW Communications.

Continue onto other sections of the LabVIEW Communications 1.1 to 2.0 Migration Guide for: 

• 802.11 Application Framework
• LTE Application Framework
• USRP Projects
• General Projects

The LabVIEW Communications product documentation provides detailed information in addition to the tasks discussed in this guide. Hardware manuals also contain valuable information about the features and performance characteristics of NI RIO devices.

The main NI support page, ni.com/support, provides quick access to manuals, KnowledgeBase documents, tutorials, example code, community forums, technical support, and customer service.