Each issue appears as a row in the table and includes the following fields:
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| 202020 Return | A former version of the bitfile is loaded onto the FPGAs of the ATCA-3671 by default NI-ATCA FPGA Modules users cannot access PCIe performance improvements and other fixes because the bifile automatically loaded onto the FPGAs is not the latest. Driver versions 16.0 to 18.0 do not offer a mechanism for updating the bitfile. Workaround: Complete the following steps to update your bitfile.
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| 202025 Return | The ATCA-3671 (Rev A) may power down after several hours of operation NI-ATCA FPGA Modules users cannot access PCIe performance improvements and other fixes because the bifile automatically loaded onto the FPGAs is not the latest. Driver versions 16.0 to 18.0 do not offer a mechanism for updating the bitfile. Workaround: Complete the following steps to reset the power regulator limit configuration.
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| 736818 Return | NI-ATCA 19.0 Runtime remains on your machine after you uninstall NI-ATCA FPGA Modules 19.0 When you uninstall NI-ATCA 19.0 FPGA Modules from NI Package Manager, the NI-ATCA Runtime is not automatically uninstalled. Workaround: To uninstall the NI-ATCA Runtime, complete the following steps.
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| 711045 Return | PCIe bandwidth changes after bitfile download When downloading a bitfile to the ATCA-3671, the PCIe link to the host system is renegotiated. This negotiation may not result in a full bandwidth connection. Instead, a link may be downtrained to a slower speed or fewer lanes. This impacts applications relying on high-rate DMA streaming (peer-to-peer, host-to-target, target-to-host) at maximum or near-maximum rates. Some 3rd-party PCs with PCIe generation 3 capabilities exacerbate this issue. Workaround: If your application requires a specific data rate for streaming, use the Check PCIe Bandwidth VI (Instrument I/O>>Instrument Drivers>>ATCA>>Advanced) to verify that the lane rate and width required is available after download. If needed, use the RIO Download invoke method to re-download the bitstream and renegotiate the bandwidth. When using non-NI host PCs, it is recommended that application-specific PCIe streaming requirements be vetted before committing to a particular host PC.
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| 709150 Return | JTAG debugging may interfere with the bitstream download process When debugging with JTAG, downloading to an FPGA or connecting to the device may disrupt the bitstream download process and interfere with communication over the PCIe connection. Workaround: If you cannot reconnect or redownload to the ATCA-3671 from a host machine after JTAG debugging, power cycle the ATCA to resolve any issues.
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| 708348 Return | FPGA enumeration fails during power-on or after bitfile download Rarely during power-on or after bitfile download, PCIe negotiation between an ATCA-3671 FPGA and a host PC fails and the device becomes inaccessible via PCIe from the host machine. This failure will also occur if a user application downloads an image to one of the ATCA FPGAs using a mechanism other than the RIO download invoke method or LabVIEW FPGA Open Session. For example, downloading images through the BPS workflow or using the NI-ATCA Remote Bitstream Download VI will cause this failure. Workaround: Use the NI-ATCA Remote Download VI to force a PCIe link reset and restart the host computer.
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| 698625 Return | Failed ATCA-3671 compile reports "ERROR::90 - The BRAM instance <instance> could not be found in the netlist during synthesis" When an ATCA-3671 LVFPGA compiles using the AIO-3691 or AIO-3692 CLIP files, the log may report multiple instances of "ERROR::90 - The BRAM instance could not be found in the netlist. Please verify the instance name in the BMM file and the netlist." These errors occur because multiple microblaze cores are used in the design but BRAM is initialized in a single step. They do not indicate an actual problem with the BRAM initialization and will not cause compiles to fail. Workaround: Check the end of the Xilinx log for the failed compile to determine the reason that the compile failed. Look for errors other than ERROR::90.
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| 635892 Return | NI-ATCA FPGA Driver Software reports error -61214 when attempting to communicate with the device When attempting to access controls, indicators, FIFOs, or IRQs, you may receive error -61214, "LabVIEW FPGA: For bitfiles that allow removal of implicit enable signals in single-cycle Timed Loops, LabVIEW FPGA does not support this method prior to running the bitfile." This error can occur after the following sequence of events:
Workaround: Implement one of the following solutions:
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| 615894 Return | DRAM bank throughput is asymmetric The middle DRAM banks on the ATCA-3671 demonstrate higher throughput than the edge banks. Refer to the nominal throughput numbers below. Write-only throughput: Middle: 9.04GBps; Edge: 8.46GBps Read-only throughput: Middle: 9.13GBps; Edge: 8.70GBps Workaround: N/A
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Contact NI regarding this document or issues in the document. If you contact NI in regards to a specific issue, reference the ID number given in the document. The ID number contains the current issue ID number as well as the legacy ID number (use the current ID number when contacting NI). You can contact us through any of the normal support channels including phone, email, or the discussion forums. Visit the NI Website to contact us. Also contact us if you find a workaround for an issue that is not listed in the document.