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This content provides support for older products and technology, so you may notice outdated links or obsolete information about operating systems or other relevant products.
This document contains the LabVIEW 2011 FPGA Module known issues that were discovered before and since the release of LabVIEW 2011 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.
The LabVIEW 2011 Platform Known Issues contains a full listing of known issues, including LabVIEW toolkits and modules.
The Known Issues Document is divided into two separate tables. The following section displays the issues by issue category.
Please refer to Developer Zone Article LabVIEW Known Issues Categories Defined for an explanation of the categories and what types of issues are in each category.
For those who wish to locate the newly reported issues, we have also have published a section of the known issues table sorted by the date the issue was added to the document.
Feel free to contact NI regarding this document or issues in the document. If you are contacting NI in regards to a specific issue, be sure to reference the ID number given in the document to the NI representative. The ID number contains the current issue ID number as well as the legacy ID number (use the current ID number when contacting National Instruments). You can contact us through any of the normal support channels including phone, email, or the discussion forums. Visit the NI Website to contact us. Also consider contacting us if you find a workaround for an issue that is not listed in the document so that we can add the workaround to the document.
The following items are known issues in LabVIEW 2010 and 2010SP1 FPGA Module sorted by Category.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| Building and Distributing LabVIEW Applications | ||||||
| 171971 Return | TCP must be installed Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server. Workaround: TCP must be installed.
| |||||
| 93395 4GIHITXE Return | Modifying conditional disable symbols requires recompile If you modify the conditional disable symbols in a project, the FPGA Module requires you to recompile the FPGA VI even if the FPGA VI does not use Conditional Disable structures. Workaround: Recompile the FPGA VI.
| |||||
| 95971 Return | Error compiling empty external clock loop If you compile an FPGA VI that contains only an empty loop configured to use an external clock, the FPGA Module returns an error. Workaround: Do not compile an FPGA VI that contains only an empty loop configured to use an external clock.
| |||||
| 308548 Return | The Xilinx map program can crash if a file named "map" can be found anywhere on your system path. When LabVIEW FPGA is running a compile, if a file named "map" can be found anywhere on your system path, then compilation will fail partway through. When compilation fails for this reason, the Xilinx log will contain an error with a message similar to the following: C:\PROGRA~2\MICROS~1.0\VC\include\map' is not recognized as an internal or external command, operable program or batch file. Process "Map" failed Workaround: There are two workarounds. 1. Make a copy of the map.exe executables in your Xilinx bin directories. For example, for Xilinx 12.4 32-bit and 64-bit, make a copy of c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt\map.exe in c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt\map and a copy of c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt64\map.exe in c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt64\map. 2. Remove from your system path any directories that have files whose names match those of Xilinx executables but have no extension (i.e. map, par, trce, coregen). Restart the compile worker if it is running.
| |||||
| 247993 Return | Removing a C-Series Module in a Project Forces Recompilation Removing a module from a Chassis in a LabVIEW FPGA Project will force a recompilation, even if all VIs in the Build Specification's hierarchy do not reference the module. Workaround: NA
| |||||
| 354689 Return | Customer designs may fail with an over-mapping error if Output data and enable are synchronous to different clocks Users can place Output Data and Enable nodes in different clock domains. This results in a Tri-state buffer on the FPGA that is enabled by a signal in the different clock domain than the data signal. Some FPGA families may not support this configuration, and user's design may fail to compile with an over-mapping error in some situations. For a Virtex 2 compile, the error may look similar to the attached Compilation Error.png file. The situation where it might fail for Virtex 2 is when two IO Nodes are mapped over two adjacent IOBs and the Data and Enable flops for the IOs are synchronous to 3 or more different clocks. Workaround: The workaround is to modify the VI. Move the Output Enable node into the same clock domain as the Output Data node.
| |||||
| 313960 Return | DSP48s Are Not Properly Optimized with Integer Constants in LabVIEW FPGA 2011 LabVIEW FPGA 2011 does not properly optimize the amount of DSP48s in some cases. Unused data bits in integer constants cause more DSP48s to be used than are necessary. This can cause timing and resource utilization errors during compilation. Workaround: In place of integer constants use fixed point (FXP) constants when wired to functions that require DSP48s. LabVIEW handles DSP48 optimization for FXP numbers better than integers.
| |||||
| Compatibility | ||||||
| 156070 Return | Save for Previous of FPGA IO Nodes from 2009 and later to 8.6 and earlier can cause broken run arrow. When performing a Save for Previous on FPGA projects containing IO items that are in version 2009 or later, IO Nodes can break when converting to version 8.6 and earlier. Workaround: Redrop IO Nodes.
| |||||
| 288024 Return | VI-defined memory loses initial values after Save for Previous for 8.6 and earlier. When saving an FPGA project from version 2009 or later to version 8.6 or earlier, VI-defined memory items lose any initial values. Workaround: Recreate the initial values in the previous version.
| |||||
| Controls and Indicators | ||||||
| 307714 Return | Silver controls are not available on Controls palette in FPGA VI context. The Silver controls palette is not available for VIs opened under an FPGA target. Workaround: Create controls/indicators on VIs under the My Computer context and then move the VI to the FPGA context.
| |||||
| External Code | ||||||
| 238241 Return | When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page. When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page. Workaround: The wizard only extracts information from the top-level VHDL file, so add another VHDL wrapper that instantiates the original wrapper. In the new wrapper, do not mention the entity attribute.
| |||||
| 283397 Return | All CLIP vhd files must have a lowercase vhd extension. CLIP vhd files are required to have a lower case extension or there will be an odd behavior during compiles. Workaround: Define the VHD files with a lower case extension in the clip XML file.
| |||||
| 303501 Return | Xilinx compile errors occur when using the IP Integration Node to integrate VHDL with string constants defined in package files in the generic and/or port declaration. When you use IP Integration Node to wrap your IP and the top-level VHDL has constants or types in the generic and/or port declaration which are defined in your package files, a Xilinx error will be reported saying that the string constants are not declared when you compile. Workaround: Add full namespace to the string constants in the generic and/or port declaration of the top-level VHDL.
| |||||
| 304569 Return | The post-synthesis model of a ngc file will fail to simulate if the file name of the ngc file is different from the ngc component name. When performing cycle accurate simulation with IP Integration node, the post-synthesis model of a ngc file will fail to simulate if the file name of the ngc file is different from the ngc component name. Workaround: Make sure the ngc file name is the name of the ngc component name.
| |||||
| 297138 Return | The length of the port name in the top-level VHDL file of a CLIP should not exceed 22 letters. The length of the port name in the top-level VHDL file of a CLIP should not exceed 22 letters. Or else, the long name will be truncated by LabVIEW FPGA, which will lead to compilation failure. Workaround: Change the port name to be shorter than 22 letters.
| |||||
| 300339 Return | Estimated Device Utilization Incorrect or Not Available for Certain Projects and Targets Projects for NI FlexRIO targets or projects with user-defined IP that includes pre-compiled netlists (such as .ngc files) may show incorrect results in the "Estimated device utilization (pre-synthesis)" report. The numbers shown of used slice registers and slice LUTs may be smaller-than-expected (possible even zero). Workaround: This problem only affects "pre-synthesis" resource estimations. Correct utilization data can always be obtained by compiling the project, which provides both the correct "Estimated device utilization (synthesis)" and "Final device utilization (map)" reports. If the "pre-synthesis" estimated results are absolutely necessary, the correct pre-synthesis estimation of used slice registers and slice LUTs can be found within the Xilinx log at the end of the PlanAhead section and before XstSynthesis.
| |||||
| 357304 Return | LabVIEW FPGA Derived Clocks Do Not Behave Properly Within FlexRIO Adapter Module CLIP The enable signal to a BUFGCE of a derived clock requires the derived clock to be preset (out of a BUFG from the DCM). This is problematic because the adapter module goes through a power cycle during the download, reset, and close with reset methods. This causes the external clock from CLIP to shut off, and the clock remains turned off until sometime after the adapter module resumes power. In Short: 1. When reset is asserted, the FAM CLIP disables it's clock, and the derived clock's BUFGCE is still enabled even though there is no clock at the input of the DCM. 2. The derived clock valid signal remains high out of reset even though the CLIP has the source clock valid signal low (it's reset state) and has not yet supplied a clock. Workaround: Derive all needed clocks within the CLIP itself and disable support for user derived clocks in LabVIEW FPGA via the CLIP XML.
| |||||
| Functions, VIs, and Express VIs | ||||||
| 150867 Return | "Not supported for current target" message may occur when Preallocate Arrays is not set. The "Not supported for current target" error may be displayed for FPGA Analysis functions when the FPGA Preallocate Arrays option is not set. The actual error is that this option must be selected. Workaround: In VI Properties check the Preallocate Arrays option.
| |||||
| 151047 Return | High-Throughput Math Library node fails to compile if pipeline stage exceeds 64 If the number of pipeline stages exceeds 64, the compile will report "Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more." This usually happens in configurations of high-throughput math library nodes where the output data width is 64 and throughput is 1 cycle/sample inside SCTL. Workaround: Reduce the pipeline stages by reducing the output word length or the throughput. If more than 64 pipeline stages are needed, please contact National Instruments support.
| |||||
| 217824 Return | FIFOs with built-in control are not supported with cycle-accurate simulation. When attempting to use full diagram simulation on a design using FIFOs with built-in control logic, there is no simulation model for these elements. Workaround: Use a conditional disable structure around the built-in FIFOs when using full diagram simulation.
| |||||
| 232504 Return | Compilation on Spartan-6 FPGAs fails when compound add is placed before Loop Condition terminal. Compilations for Spartan-6 targets can fail is a compound add function is placed directly before the Loop Condition terminal in a single-cycle timed loop. Workaround: Change number of inputs to compound add to an even number or replace with regular add functions.
| |||||
| 296185 Return | Interleaving two arrays with different fixed-point configurations returns a code generation error. When using the Interleave Arrays function on a LabVIEW FPGA VI, if the arrays are of the same fixed length, but the fixed-point configurations of the elements are different, code generation will fail. Workaround: Change the fixed point configuration of the two arrays to be the same using "To Fixed-Point".
| |||||
| 320103 Return | LabVIEW crashes when compiling an FPGA VI containing an error cluster wired to a Boolean function. A new feature added to LabVIEW 2011 was the ability to wire an error cluster directly to a Boolean function. Compiling an FPGA VI that contains this feature will cause LabVIEW to crash. Workaround: Unbundle the error wire and wire the status element to the Boolean function manually.
| |||||
| 310755 Return | FIFO Name Discrepancies may Cause Error -61206 If a DMA FIFO has a mismatch in capitalization between its name and what the FPGA interface expects, then error -61206: "The configured item does not exist". Workaround: Use lower case letters for FIFO names
| |||||
| 313940 Return | The Mean,Variance, and Standard Deviation Express VI may Return Invalid Values Due to a roundoff error that may occur with small variance values, the Mean,Variance, and Standard Deviation Express VI may return incorrect results. Workaround: Edit the SubVI to adapt it to a configuration that meets your application's specific needs. For more information, please see the following forum thread: http://forums.ni.com/t5/LabVIEW/labview-2010-FPGA-problem-with-mean-variance-SubVI/td-p/1659110
| |||||
| 357204 Return | Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations The Compound Arithmetic function may execute operations in a different order on the FPGA than on the desktop, producing slightly different results for floating-point operations. The differences include small rounding discrepancies as well as NaN and Inf behavior. Workaround: Decompose the Compound Arithmetic Function into individual arithmetic functions to force the order of operations to conform to what you expect.
| |||||
| Installation and Activation | ||||||
| 236642 Return | LabVIEW's install directory can't have multibyte characters for the Xilinx tools to work. Local compiles with the Xilinx tools are not possible if LabVIEW's directory contains multibyte characters. If it is the default program files windows path then everything will work fine. Workaround: You can use the remote compile feature to use another machine to do your compilations if you run into this issue. It can be a Japanese machine, just make sure that the LabVIEW directory doesn't have multibyte characters.
| |||||
| 306365 Return | Some Xilinx IP palette functions require separate licensing from Xilinx For some functions on the Xilinx IP palette, when launching Xilinx CoreGenerator, you may see a dialog indicating the core is not licensed. To obtain licenses for these cores, visit http://www.xilinx.com/products/intellectual-property/index.htm. Workaround: NA
| |||||
| LabVIEW Project | ||||||
| 223670 Return | Compiling a VI in one FPGA context creates a code generation error if the VI is open and broken in another FPGA context. The compilation of a VI may return an error saying the VI is broken if the same VI is open and broken in another FPGA context. The error occurs at the beginning of stage 1 of the compilation. Workaround: Close the broken copies of the VI in the other FPGA contexts.
| |||||
| 277539 Return | FPGA VI remains running on the target while the VI is open in edit mode. While the top-level FPGA VI is running, you can open a reentrant SubVI from the block diagram and change to edit-mode from the clone. If you break the SubVI in edit-mode, the top-level FPGA VI will also break, but the VI will remain running on the target. If you fix the SubVI, both VIs will no longer be broken and the FPGA VI cannot be stopped. Workaround: Reboot the target.
| |||||
| 304855 Return | Editing project items causes LabVIEW to search for missing VIs. Editing project items under an FPGA target can cause LabVIEW to search for VIs included in the project under the FPGA target if the VI cannot be found on disk. Workaround: Remove the missing VI from the project or update the project to load the VI from the correct location.
| |||||
| Miscellaneous | ||||||
| 172016 Return | Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality. Workaround: Refer to the KnowledgeBase (http://digital.ni.com/public.nsf/websearch/91A1EA23DB25BE4386256E54007AE9E8?OpenDocument) for more information about correcting this problem.
| |||||
| 226029 Return | The behavior of the Run button can be confusing when using the THIRD_PARTY_SIMULATION conditional disable symbol. Errors that normally break the Run button will not break the Run button if the error occurs within a Conditional Disable structure case defined for THIRD_PARTY_SIMULATION. In this case, you cannot build simulation exports, but you can build other build specifications. In addition, if the VI has errors outside the simulation-specific case and the Run button is broken, you will not be able to build a Simulation Export build specification. Workaround: * If the Run button is not broken but the simulation-specific code contains errors, LabVIEW produces code generation errors when you try to build the Simulation Export build specification. Fix the broken code before building the simulation export. * If the Run button is broken because of code outside of a case defined for THIRD_PARTY_SIMULATION , you have the following options to work around the issue before building a Simulation Export build specification: 1) Fix the error condition in the code. 2) Use the Diagram Disable structure to disable the broken or target-specific code. 3) Define your own custom conditional disable symbol in the project for the FPGA target you are using, and place the broken code in that case of the Conditional Disable structure.
| |||||
| 197816 Return | Virtex 6 design with PLLs simulation run forever Currently there is not a mechanism to stop the Virtex 6 PLL from running, which can cause the simulation to continue running when the "Run All" command is used in the simulator. Workaround: You can use one of the following options to stop the simulation: * Add an assertion failure to the of end your test bench. * Run the test bench for a specified amount of time.
| |||||
| Performance | ||||||
| 236075 Return |
R-Series simulation error when loading waveform script that includes DIO ports /TargetTopLevelSim_Instance/thewindowx/thevi/../Conn0Port0'.
| |||||
| 287790 Return | "Compile Worker has stopped working" error message on launch. When launching the Compile Worker for the first time after installation, this error may occur due to a bug in the .NET framework causing a hang. Workaround: Restart the Compile Worker.
| |||||
| 294273 Return | Using long VI names may cause Error 6 during FPGA code generation. If a VI name or path is too long, you may see the following error during code generation: Error 6:Copy VI Hierarchy With FPGA Side Effects Workaround: Shorten the FPGA VI name or path.
| |||||
| 300201 Return | When using the NI-Farm toolkit and having a CompileWorker.exe with multiple simultaneous jobs there may be hangs. When using the NI-Farm toolkit with a single CompileWorker.exe compiling simultaneous jobs, it is possible for one or more of the jobs to hang. Workaround: Restart the hung job.
| |||||
| 304548 Return | Compilation Status dialog is unresponsive after computer has hibernated or been disconnected from a large job When compiling on a remote machine, if client computer disconnects or goes into hibernation (sleep), the Compilation Status dialog may become unresponsive after reconnecting or when the client computer wakes up. The Elapsed Time may still be increasing, and the status icon may be spinning rapidly. LabVIEW will be using more memory and more CPU resources. Other VIs and project windows in LabVIEW should still be responsive. Workaround: Save all your files and restart LabVIEW. Open the corresponding project, right-click on the Build Specification, and choose Reconnect to Compilation. You should be able to retrieve your compilation and create a bitfile.
| |||||
| 304799 Return | If a compilation fails with a communication error, the bitfile may be lost. If a communication error occurs while compiling a LabVIEW FPGA VI, it is possible you may not be able to reconnect to the compilation. Workaround: Rebuild the LabVIEW FPGA VI.
| |||||
| Upgrade - Behavior Change | ||||||
| 317617 Return | Disabled Front Panel Items Use FPGA Resources Front Panel Array Items that are located within a disabled state of a diagram disable structure are not removed before compilation. This change is a result of a bug-fix that brought LabVIEW FPGA into line with standard LabVIEW behavior. The implications of this are two-fold: 1. You may now run into resource over-mapping compilation errors, especially if large array items are present on the Front Panel. 2. You may now run into timing violation compilation errors if a Front Panel item is tied to a fixed resource within a Single Cycle Timed Loop due to routing delays between fixed resources (I/O) Workaround: N/A
| |||||
| Upgrade - Migration | ||||||
| 107560 Return | Interrupt VIs saved to previous versions of LabVIEW are broken If you save an FPGA VI that contains an Interrupt VI to a previous version of LabVIEW and open the FPGA VI in a previous version of LabVIEW, the FPGA VI is broken because the Interrupt VI is not executable. Workaround: You can delete the Interrupt VI and replace it with an Interrupt VI from the current version to resolve the issue.
| |||||
| 257184 Return | Upgrading with clocks from CLIP can change the configured clocks. When upgrading, if a design uses CLIP clocks, the configuration of these clocks may be reset. Workaround: Reconfigure the CLIP clocks in the project.
| |||||
| 276311 Return | Upgrading from LabVIEW FPGA 2009 may cause designs using DSP48E components to overmap. When upgrading from LabVIEW FPGA 2009, it is possible that designs that fit on the FPGA target previously will fail to compile due to overmapping of DSP48E components. This is due to a change in the Xilinx compile process from version 10.1 to 11.x and later. Workaround: Use High-Throughput multiplies configured to use Look-Up Tables to reduce the number of DSP48Es used for multiplication functions.
| |||||
| 284873 Return | Upgrading host VIs saved with Execute VI on Development Computer causes prompt to find niLvFpgaEmulationMode.ctl. When a host VI was last saved with the FPGA target configured to Execute VI on Development Computer, a search dialog will be displayed looking for niLvFpgaEmulationMode.ctl. Workaround: Reconfigure the target to execute on the FPGA and then back to the development computer.
| |||||
The following items are known issues in LabVIEW 2010 and 2010SP1 FPGA Module sorted by Date.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| 107560 Return | Interrupt VIs saved to previous versions of LabVIEW are broken If you save an FPGA VI that contains an Interrupt VI to a previous version of LabVIEW and open the FPGA VI in a previous version of LabVIEW, the FPGA VI is broken because the Interrupt VI is not executable. Workaround: You can delete the Interrupt VI and replace it with an Interrupt VI from the current version to resolve the issue.
| |||||
| 171971 Return | TCP must be installed Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server. Workaround: TCP must be installed.
| |||||
| 172016 Return | Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality. Workaround: Refer to the KnowledgeBase (http://digital.ni.com/public.nsf/websearch/91A1EA23DB25BE4386256E54007AE9E8?OpenDocument) for more information about correcting this problem.
| |||||
| 93395 4GIHITXE Return | Modifying conditional disable symbols requires recompile If you modify the conditional disable symbols in a project, the FPGA Module requires you to recompile the FPGA VI even if the FPGA VI does not use Conditional Disable structures. Workaround: Recompile the FPGA VI.
| |||||
| 95971 Return | Error compiling empty external clock loop If you compile an FPGA VI that contains only an empty loop configured to use an external clock, the FPGA Module returns an error. Workaround: Do not compile an FPGA VI that contains only an empty loop configured to use an external clock.
| |||||
| 150867 Return | "Not supported for current target" message may occur when Preallocate Arrays is not set. The "Not supported for current target" error may be displayed for FPGA Analysis functions when the FPGA Preallocate Arrays option is not set. The actual error is that this option must be selected. Workaround: In VI Properties check the Preallocate Arrays option.
| |||||
| 151047 Return | High-Throughput Math Library node fails to compile if pipeline stage exceeds 64 If the number of pipeline stages exceeds 64, the compile will report "Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more." This usually happens in configurations of high-throughput math library nodes where the output data width is 64 and throughput is 1 cycle/sample inside SCTL. Workaround: Reduce the pipeline stages by reducing the output word length or the throughput. If more than 64 pipeline stages are needed, please contact National Instruments support.
| |||||
| 156070 Return | Save for Previous of FPGA IO Nodes from 2009 and later to 8.6 and earlier can cause broken run arrow. When performing a Save for Previous on FPGA projects containing IO items that are in version 2009 or later, IO Nodes can break when converting to version 8.6 and earlier. Workaround: Redrop IO Nodes.
| |||||
| 217824 Return | FIFOs with built-in control are not supported with cycle-accurate simulation. When attempting to use full diagram simulation on a design using FIFOs with built-in control logic, there is no simulation model for these elements. Workaround: Use a conditional disable structure around the built-in FIFOs when using full diagram simulation.
| |||||
| 223670 Return | Compiling a VI in one FPGA context creates a code generation error if the VI is open and broken in another FPGA context. The compilation of a VI may return an error saying the VI is broken if the same VI is open and broken in another FPGA context. The error occurs at the beginning of stage 1 of the compilation. Workaround: Close the broken copies of the VI in the other FPGA contexts.
| |||||
| 226029 Return | The behavior of the Run button can be confusing when using the THIRD_PARTY_SIMULATION conditional disable symbol. Errors that normally break the Run button will not break the Run button if the error occurs within a Conditional Disable structure case defined for THIRD_PARTY_SIMULATION. In this case, you cannot build simulation exports, but you can build other build specifications. In addition, if the VI has errors outside the simulation-specific case and the Run button is broken, you will not be able to build a Simulation Export build specification. Workaround: * If the Run button is not broken but the simulation-specific code contains errors, LabVIEW produces code generation errors when you try to build the Simulation Export build specification. Fix the broken code before building the simulation export. * If the Run button is broken because of code outside of a case defined for THIRD_PARTY_SIMULATION , you have the following options to work around the issue before building a Simulation Export build specification: 1) Fix the error condition in the code. 2) Use the Diagram Disable structure to disable the broken or target-specific code. 3) Define your own custom conditional disable symbol in the project for the FPGA target you are using, and place the broken code in that case of the Conditional Disable structure.
| |||||
| 232504 Return | Compilation on Spartan-6 FPGAs fails when compound add is placed before Loop Condition terminal. Compilations for Spartan-6 targets can fail is a compound add function is placed directly before the Loop Condition terminal in a single-cycle timed loop. Workaround: Change number of inputs to compound add to an even number or replace with regular add functions.
| |||||
| 236075 Return |
R-Series simulation error when loading waveform script that includes DIO ports /TargetTopLevelSim_Instance/thewindowx/thevi/../Conn0Port0'.
| |||||
| 236642 Return | LabVIEW's install directory can't have multibyte characters for the Xilinx tools to work. Local compiles with the Xilinx tools are not possible if LabVIEW's directory contains multibyte characters. If it is the default program files windows path then everything will work fine. Workaround: You can use the remote compile feature to use another machine to do your compilations if you run into this issue. It can be a Japanese machine, just make sure that the LabVIEW directory doesn't have multibyte characters.
| |||||
| 238241 Return | When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page. When entity level attributes are used in a VHDL file, IP Integration Node wizard hangs on the second dialog page. Workaround: The wizard only extracts information from the top-level VHDL file, so add another VHDL wrapper that instantiates the original wrapper. In the new wrapper, do not mention the entity attribute.
| |||||
| 257184 Return | Upgrading with clocks from CLIP can change the configured clocks. When upgrading, if a design uses CLIP clocks, the configuration of these clocks may be reset. Workaround: Reconfigure the CLIP clocks in the project.
| |||||
| 276311 Return | Upgrading from LabVIEW FPGA 2009 may cause designs using DSP48E components to overmap. When upgrading from LabVIEW FPGA 2009, it is possible that designs that fit on the FPGA target previously will fail to compile due to overmapping of DSP48E components. This is due to a change in the Xilinx compile process from version 10.1 to 11.x and later. Workaround: Use High-Throughput multiplies configured to use Look-Up Tables to reduce the number of DSP48Es used for multiplication functions.
| |||||
| 277539 Return | FPGA VI remains running on the target while the VI is open in edit mode. While the top-level FPGA VI is running, you can open a reentrant SubVI from the block diagram and change to edit-mode from the clone. If you break the SubVI in edit-mode, the top-level FPGA VI will also break, but the VI will remain running on the target. If you fix the SubVI, both VIs will no longer be broken and the FPGA VI cannot be stopped. Workaround: Reboot the target.
| |||||
| 283397 Return | All CLIP vhd files must have a lowercase vhd extension. CLIP vhd files are required to have a lower case extension or there will be an odd behavior during compiles. Workaround: Define the VHD files with a lower case extension in the clip XML file.
| |||||
| 284873 Return | Upgrading host VIs saved with Execute VI on Development Computer causes prompt to find niLvFpgaEmulationMode.ctl. When a host VI was last saved with the FPGA target configured to Execute VI on Development Computer, a search dialog will be displayed looking for niLvFpgaEmulationMode.ctl. Workaround: Reconfigure the target to execute on the FPGA and then back to the development computer.
| |||||
| 287790 Return | "Compile Worker has stopped working" error message on launch. When launching the Compile Worker for the first time after installation, this error may occur due to a bug in the .NET framework causing a hang. Workaround: Restart the Compile Worker.
| |||||
| 288024 Return | VI-defined memory loses initial values after Save for Previous for 8.6 and earlier. When saving an FPGA project from version 2009 or later to version 8.6 or earlier, VI-defined memory items lose any initial values. Workaround: Recreate the initial values in the previous version.
| |||||
| 294273 Return | Using long VI names may cause Error 6 during FPGA code generation. If a VI name or path is too long, you may see the following error during code generation: Error 6:Copy VI Hierarchy With FPGA Side Effects Workaround: Shorten the FPGA VI name or path.
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| 296185 Return | Interleaving two arrays with different fixed-point configurations returns a code generation error. When using the Interleave Arrays function on a LabVIEW FPGA VI, if the arrays are of the same fixed length, but the fixed-point configurations of the elements are different, code generation will fail. Workaround: Change the fixed point configuration of the two arrays to be the same using "To Fixed-Point".
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| 300201 Return | When using the NI-Farm toolkit and having a CompileWorker.exe with multiple simultaneous jobs there may be hangs. When using the NI-Farm toolkit with a single CompileWorker.exe compiling simultaneous jobs, it is possible for one or more of the jobs to hang. Workaround: Restart the hung job.
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| 303501 Return | Xilinx compile errors occur when using the IP Integration Node to integrate VHDL with string constants defined in package files in the generic and/or port declaration. When you use IP Integration Node to wrap your IP and the top-level VHDL has constants or types in the generic and/or port declaration which are defined in your package files, a Xilinx error will be reported saying that the string constants are not declared when you compile. Workaround: Add full namespace to the string constants in the generic and/or port declaration of the top-level VHDL.
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| 304548 Return | Compilation Status dialog is unresponsive after computer has hibernated or been disconnected from a large job When compiling on a remote machine, if client computer disconnects or goes into hibernation (sleep), the Compilation Status dialog may become unresponsive after reconnecting or when the client computer wakes up. The Elapsed Time may still be increasing, and the status icon may be spinning rapidly. LabVIEW will be using more memory and more CPU resources. Other VIs and project windows in LabVIEW should still be responsive. Workaround: Save all your files and restart LabVIEW. Open the corresponding project, right-click on the Build Specification, and choose Reconnect to Compilation. You should be able to retrieve your compilation and create a bitfile.
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| 304569 Return | The post-synthesis model of a ngc file will fail to simulate if the file name of the ngc file is different from the ngc component name. When performing cycle accurate simulation with IP Integration node, the post-synthesis model of a ngc file will fail to simulate if the file name of the ngc file is different from the ngc component name. Workaround: Make sure the ngc file name is the name of the ngc component name.
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| 304799 Return | If a compilation fails with a communication error, the bitfile may be lost. If a communication error occurs while compiling a LabVIEW FPGA VI, it is possible you may not be able to reconnect to the compilation. Workaround: Rebuild the LabVIEW FPGA VI.
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| 304855 Return | Editing project items causes LabVIEW to search for missing VIs. Editing project items under an FPGA target can cause LabVIEW to search for VIs included in the project under the FPGA target if the VI cannot be found on disk. Workaround: Remove the missing VI from the project or update the project to load the VI from the correct location.
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| 306365 Return | Some Xilinx IP palette functions require separate licensing from Xilinx For some functions on the Xilinx IP palette, when launching Xilinx CoreGenerator, you may see a dialog indicating the core is not licensed. To obtain licenses for these cores, visit http://www.xilinx.com/products/intellectual-property/index.htm. Workaround: NA
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| 307714 Return | Silver controls are not available on Controls palette in FPGA VI context. The Silver controls palette is not available for VIs opened under an FPGA target. Workaround: Create controls/indicators on VIs under the My Computer context and then move the VI to the FPGA context.
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| 320103 Return | LabVIEW crashes when compiling an FPGA VI containing an error cluster wired to a Boolean function. A new feature added to LabVIEW 2011 was the ability to wire an error cluster directly to a Boolean function. Compiling an FPGA VI that contains this feature will cause LabVIEW to crash. Workaround: Unbundle the error wire and wire the status element to the Boolean function manually.
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| 297138 Return | The length of the port name in the top-level VHDL file of a CLIP should not exceed 22 letters. The length of the port name in the top-level VHDL file of a CLIP should not exceed 22 letters. Or else, the long name will be truncated by LabVIEW FPGA, which will lead to compilation failure. Workaround: Change the port name to be shorter than 22 letters.
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| 300339 Return | Estimated Device Utilization Incorrect or Not Available for Certain Projects and Targets Projects for NI FlexRIO targets or projects with user-defined IP that includes pre-compiled netlists (such as .ngc files) may show incorrect results in the "Estimated device utilization (pre-synthesis)" report. The numbers shown of used slice registers and slice LUTs may be smaller-than-expected (possible even zero). Workaround: This problem only affects "pre-synthesis" resource estimations. Correct utilization data can always be obtained by compiling the project, which provides both the correct "Estimated device utilization (synthesis)" and "Final device utilization (map)" reports. If the "pre-synthesis" estimated results are absolutely necessary, the correct pre-synthesis estimation of used slice registers and slice LUTs can be found within the Xilinx log at the end of the PlanAhead section and before XstSynthesis.
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| 357304 Return | LabVIEW FPGA Derived Clocks Do Not Behave Properly Within FlexRIO Adapter Module CLIP The enable signal to a BUFGCE of a derived clock requires the derived clock to be preset (out of a BUFG from the DCM). This is problematic because the adapter module goes through a power cycle during the download, reset, and close with reset methods. This causes the external clock from CLIP to shut off, and the clock remains turned off until sometime after the adapter module resumes power. In Short: 1. When reset is asserted, the FAM CLIP disables it's clock, and the derived clock's BUFGCE is still enabled even though there is no clock at the input of the DCM. 2. The derived clock valid signal remains high out of reset even though the CLIP has the source clock valid signal low (it's reset state) and has not yet supplied a clock. Workaround: Derive all needed clocks within the CLIP itself and disable support for user derived clocks in LabVIEW FPGA via the CLIP XML.
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| 308548 Return | The Xilinx map program can crash if a file named "map" can be found anywhere on your system path. When LabVIEW FPGA is running a compile, if a file named "map" can be found anywhere on your system path, then compilation will fail partway through. When compilation fails for this reason, the Xilinx log will contain an error with a message similar to the following: C:\PROGRA~2\MICROS~1.0\VC\include\map' is not recognized as an internal or external command, operable program or batch file. Process "Map" failed Workaround: There are two workarounds. 1. Make a copy of the map.exe executables in your Xilinx bin directories. For example, for Xilinx 12.4 32-bit and 64-bit, make a copy of c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt\map.exe in c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt\map and a copy of c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt64\map.exe in c:\NIFPGA\programs\xilinx12_4\ISE\bin\nt64\map. 2. Remove from your system path any directories that have files whose names match those of Xilinx executables but have no extension (i.e. map, par, trce, coregen). Restart the compile worker if it is running.
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| 310755 Return | FIFO Name Discrepancies may Cause Error -61206 If a DMA FIFO has a mismatch in capitalization between its name and what the FPGA interface expects, then error -61206: "The configured item does not exist". Workaround: Use lower case letters for FIFO names
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| 313940 Return | The Mean,Variance, and Standard Deviation Express VI may Return Invalid Values Due to a roundoff error that may occur with small variance values, the Mean,Variance, and Standard Deviation Express VI may return incorrect results. Workaround: Edit the SubVI to adapt it to a configuration that meets your application's specific needs. For more information, please see the following forum thread: http://forums.ni.com/t5/LabVIEW/labview-2010-FPGA-problem-with-mean-variance-SubVI/td-p/1659110
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| 357204 Return | Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations The Compound Arithmetic function may execute operations in a different order on the FPGA than on the desktop, producing slightly different results for floating-point operations. The differences include small rounding discrepancies as well as NaN and Inf behavior. Workaround: Decompose the Compound Arithmetic Function into individual arithmetic functions to force the order of operations to conform to what you expect.
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| 197816 Return | Virtex 6 design with PLLs simulation run forever Currently there is not a mechanism to stop the Virtex 6 PLL from running, which can cause the simulation to continue running when the "Run All" command is used in the simulator. Workaround: You can use one of the following options to stop the simulation: * Add an assertion failure to the of end your test bench. * Run the test bench for a specified amount of time.
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| 247993 Return | Removing a C-Series Module in a Project Forces Recompilation Removing a module from a Chassis in a LabVIEW FPGA Project will force a recompilation, even if all VIs in the Build Specification's hierarchy do not reference the module. Workaround: NA
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| 317617 Return | Disabled Front Panel Items Use FPGA Resources Front Panel Array Items that are located within a disabled state of a diagram disable structure are not removed before compilation. This change is a result of a bug-fix that brought LabVIEW FPGA into line with standard LabVIEW behavior. The implications of this are two-fold: 1. You may now run into resource over-mapping compilation errors, especially if large array items are present on the Front Panel. 2. You may now run into timing violation compilation errors if a Front Panel item is tied to a fixed resource within a Single Cycle Timed Loop due to routing delays between fixed resources (I/O) Workaround: N/A
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| 354689 Return | Customer designs may fail with an over-mapping error if Output data and enable are synchronous to different clocks Users can place Output Data and Enable nodes in different clock domains. This results in a Tri-state buffer on the FPGA that is enabled by a signal in the different clock domain than the data signal. Some FPGA families may not support this configuration, and user's design may fail to compile with an over-mapping error in some situations. For a Virtex 2 compile, the error may look similar to the attached Compilation Error.png file. The situation where it might fail for Virtex 2 is when two IO Nodes are mapped over two adjacent IOBs and the Data and Enable flops for the IOs are synchronous to 3 or more different clocks. Workaround: The workaround is to modify the VI. Move the Output Enable node into the same clock domain as the Output Data node.
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| 313960 Return | DSP48s Are Not Properly Optimized with Integer Constants in LabVIEW FPGA 2011 LabVIEW FPGA 2011 does not properly optimize the amount of DSP48s in some cases. Unused data bits in integer constants cause more DSP48s to be used than are necessary. This can cause timing and resource utilization errors during compilation. Workaround: In place of integer constants use fixed point (FXP) constants when wired to functions that require DSP48s. LabVIEW handles DSP48 optimization for FXP numbers better than integers.
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Document last updated on 7/12/2012