Accelerate Time to Market with Highly Parallel Wafer-Level Reliability
Semiconductor device geometries are shrinking and becoming more complex, while major technology trends such as autonomous vehicles are placing additional pressure on the semiconductor supply chain to provide higher assurances of product quality. In order to keep up with these challenging demands and still release stable technology nodes ahead of the competition, semiconductor wafer-process engineers need more reliability-measurement data—and they need it faster than ever before.
A wafer-level reliability (WLR) solution must address these key requirements:
- Support wafer technology node development, process integration, and process monitoring
- Quickly generate sufficient amounts of reliability-measurement data to build accurate statistical models and empower data-driven decisions
- Comply with JEDEC standards for common failure mechanisms (TDDB, HCI, and BTI/NBTI, Vramp, Jramp, etc.)
- Decrease total WLR test time and accelerate data velocity
- Maximize efficiency of capital expenditures and fab floor space
Semiconductor Wafer-Level Reliability Solution
- Highly parallel WLR solution optimized for channel density and measurement speed
- Up to 48 PXIe-4135 fA-class SMU channels in a single parametric test system
- Modular and independent SMUs with a true SMU-per-pin architecture
- Specialized, JEDEC-compliant application software including an industry-standard test sequencer, device and wafer mapping, customizable operator interface, prober automation, and more
Solution Advantages
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Shorter WLR test cycles—from months to days—with industry-leading parallelism and measurement speed
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Configurable and upgradeable channel count in a highly flexible SMU-per-pin architecture
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Perform JEDEC reliability tests quickly and simply with our WLR Test Soft Front Panel and APIs
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Optional add-ons for remote systems management and data analytics
WLR Test Software: Powerful Application Software & APIs
Reliability Insight Made Simple
Learn how NI's WLR Test Software makes it simple to perform JEDEC reliability tests with a customizable operator interface, industry-standard test sequencer, and abstracted parallelism and multithreading functionality.
“The test-time reduction using this SMU-per-pin method is nothing short of spectacular, and wouldn’t be possible with large, traditional box SMUs. Our method eliminated switching and serialized-measurement time, reducing total test time to that of testing a single test point.”
-Bart De Wachter, Semiconductor Technology and Systems Group Researcher, imec
BUILD YOUR SOLUTION WITH THE NI ECOSYSTEM
NI offers a variety of solution integration options customized to your application-specific requirements. You can use your own internal integration teams for full system control or leverage the expertise of NI and our worldwide NI Partner Network to obtain a turnkey solution.
The NI Partner Network is a global community of domain, application, and overall test development experts working closely with NI to meet the needs of the engineering community. NI Partners are trusted solution providers, systems integrators, consultants, product developers, and services and sales channel experts skilled across a wide range of industries and application areas.
NI works with customers throughout the life of an application, delivering training, technical support, consultation and integration services, and maintenance programs. Teams can discover new skills by participating in NI-specific and geographic user groups and build proficiency with online and in-person training.
Semiconductor Wafer-Level Reliability Solution Brochure
Learn about NI's Semiconductor Wafer-Level Reliability Solution.
An NI Partner is a business entity independent from NI and has no agency or joint-venture relationship and does not form part of any business associations with NI.