Wafer-Level Parametric Test
Wafer-level test engineers need to reduce test time without sacrificing measurement quality and accuracy.
A Smarter Approach to Wafer-Level Parametric Test
As IC manufacturers continue to introduce new and innovative processes with decreasing device geometries, they need to ensure the additional complexity from these changes does not affect the long-term reliability of their ICs. As technologies evolve at a rapid pace, semiconductor manufacturers must increase the amount of reliability data they collect and analyze while decreasing the cost of test. When faced with this problem of more data at a lower cost, many reliability engineers find they cannot solve it using traditional reliability solutions, so they are turning toward modular, flexible solutions that can scale to fit their needs.
NI Semiconductor Brochure
Learn more about how you can lower your test cost with a platform-based approach to semiconductor test.
Featured Content
imec Reduces Wafer-Level Parametric Testing Cycle From 1 Month to 3 Days
Use the PXI platform to reduce test time, decrease cost by 75 percent, and perform process experiments that were previously impossible.
Build Highly Parallel Wafer-Level Reliability Systems With the PXI Platform
PXI provides the foundation for high-uptime, SMU-per-pin wafer-level reliability systems powered by the latest commercial processors and best-in-class PXI SMU portfolio.
Advantages of NI SMUs
NI SMUs combine the power and measurement performance of traditional box SMUs with NI technology that makes them smaller, faster, and more flexible.
Products and Solutions
APPLICATION RESOURCE
PXI Platform Resource Kit
Learn the basics of the PXI platform for semiconductor characterization with architectural notes, relevant case studies, and performance metrics.