PID

Implements a single-precision floating-point PID algorithm for PID applications with high-speed control and/or high channel count on an FPGA target. You can use this VI to create single-channel, multi-channel, and multi-rate control applications.

The PID algorithm features control action range and uses an integrator anti-windup calculation to limit the effect of the integral action during transients. The PID algorithm also features bumpless controller output for PID gain changes.


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The PID VI calculates the output, u(k), according to the following equations:

where

Kp is proportional gain Ki is integral gain Kd is derivative gain a is filter coefficient SP is setpoint beta is proportional weighting PV is process variable gamma is derivative weighting

Examples

Refer to the following example files included with LabVIEW FPGA Module.

  • labview\examples\CompactRIO\FPGA Fundamentals\FPGA Math and Analysis\Floating-point PID\Multi-Channel PID\Multi-Channel PID.lvproj
  • labview\examples\CompactRIO\FPGA Fundamentals\FPGA Math and Analysis\Floating-point PID\Multi-Rate PID\Multi-Rate PID.lvproj
  • labview\examples\R Series\FPGA Fundamentals\FPGA Math and Analysis\Floating-point PID\Multi-Channel PID\Multi-Channel PID.lvproj
  • labview\examples\R Series\FPGA Fundamentals\FPGA Math and Analysis\Floating-point PID\Multi-Rate PID\Multi-Rate PID.lvproj