NI 5160/5162 Clocking

The clock circuitry on the NI 5160/5162 offers versatile clocking options with the ability to use either the internal or external sources for sample clocks and reference clocks.  The following diagram shows the clocking options of the NI 5160/5162.

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Sample Clock

The sample clock is sent to the ADC, where it is divided by 2 and distributed to the 4 ADC quadrants.  The sample clock is divided by 16 and sent to the digitizer acquisition engine.  The NI 5160/5162 can decimate sample clocks (internal or external) by an integer divisor.

Internal Sample Clock

The internal 2.5 GHz sample clock is phase locked to the onboard 10 MHz oscillator by default.  Alternatively, the sample clock may be phase locked with the PXI Express 10 MHz clock or an external reference clock provided through the SMB CLK IN connector on the front panel of the device.  The internal sample clock is decimated using the Min Sample Rate property.

External Sample Clock

Some applications may require sampling at specific sample rates that cannot be achieved by decimating the internal sample clock by an integer divisor. In these cases the digitizer can accept an external sample clock. External clocking also provides another method to synchronize the digitizer to other devices in a measurement system by distributing a common clock to multiple devices. An external sample clock can be supplied to the digitizer from the front panel SMB CLK IN connector.  Refer to the hardware specifications document for external sample clock requirements.

Note   Exporting the external sample clock is not supported on the NI 5160/5162.

You can specify an external sample clock for use by configuring the Sample Clock Timebase Source and Sample Clock Timebase Rate properties. An external sample clock is decimated or multiplied by the values of the Sample Clock Timebase Divisor and Sample Clock Timebase Multiplier properties, respectively.

Reference Clock

The reference clock is used in the digitizer's phase-locked loop (PLL) circuit to lock the sample clock to the reference clock. The frequency stability of the sample clock matches that of the reference clock when the two are phase locked. This digitizer can accept a reference clock from the front panel (CLK IN) as well as from PXI_CLK10. A reference clock provided to the CLK IN SMB connector is typically 10 MHz. The PXI_CLK10 signal is always a 10 MHz clock. Phase locking can lock sample clocks of multiple devices to the same reference clock. For PCI devices, the onboard 10 MHz oscillator is the default reference clock. For PXI and PXIe devices, the default reference clock behavior varies by device.

Note   Locking to a reference clock is not valid when using external sample clocking.

Exporting Reference Clock

You can export the reference clock to synchronize other instruments to the NI 5160/5162. For more information on exporting the reference clock, refer to the NI 5160/5162 Routing Matrix.